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公开(公告)号:US10521287B2
公开(公告)日:2019-12-31
申请号:US16153225
申请日:2018-10-05
Applicant: Seagate Technology LLC
Inventor: Antoine Khoueir , Stacey Secatch , Kevin Gomez , Ryan Goss
Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
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公开(公告)号:US10095568B2
公开(公告)日:2018-10-09
申请号:US15498595
申请日:2017-04-27
Applicant: Seagate Technology, LLC
Inventor: Antoine Khoueir , Stacey Secatch , Kevin Gomez , Ryan Goss
Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
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公开(公告)号:US20190042343A1
公开(公告)日:2019-02-07
申请号:US16153225
申请日:2018-10-05
Applicant: Seagate Technology LLC
Inventor: Antoine Khoueir , Stacey Secatch , Kevin Gomez , Ryan Goss
CPC classification number: G06F11/076 , G06F11/073 , G06F11/1072 , G06F12/0246 , G06F2212/1016 , G06F2212/1032 , G06F2212/7205 , G06F2212/7207 , G11C11/5642 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3459
Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
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公开(公告)号:US20180225164A1
公开(公告)日:2018-08-09
申请号:US15498595
申请日:2017-04-27
Applicant: Seagate Technology, LLC
Inventor: Antoine Khoueir , Stacey Secatch , Kevin Gomez , Ryan Goss
CPC classification number: G06F11/076 , G06F11/073 , G11C16/16 , G11C16/26 , G11C16/3459
Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
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