公开(公告)号：US20190354498A1

公开(公告)日：2019-11-21

申请号：US15982210

申请日：2018-05-17

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Dana Lynn Simonson ,  AbdelHakim Alhussien ,  Erich Franz Haratsch ,  Steven Howe

IPC: G06F13/26 ,  G06F9/48 ,  G06F13/16

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.

公开(公告)号：US10509747B2

公开(公告)日：2019-12-17

申请号：US15982210

申请日：2018-05-17

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Dana Lynn Simonson ,  AbdelHakim Alhussien ,  Erich Franz Haratsch ,  Steven Howe

IPC: G06F13/26 ,  G06F13/16 ,  G06F9/48

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.