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公开(公告)号：US20200036392A1
公开(公告)日：2020-01-30
申请号：US16589564
申请日：2019-10-01
摘要： Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).
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公开(公告)号：US10509747B2
公开(公告)日：2019-12-17
申请号：US15982210
申请日：2018-05-17
发明人： David Scott Ebsen , Dana Lynn Simonson , AbdelHakim Alhussien , Erich Franz Haratsch , Steven Howe
摘要： A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.
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公开(公告)号：US20180287635A1
公开(公告)日：2018-10-04
申请号：US15478895
申请日：2017-04-04
发明人： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC分类号： H03M13/11
CPC分类号： H03M13/1111
摘要： Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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公开(公告)号：US10409518B1
公开(公告)日：2019-09-10
申请号：US15493102
申请日：2017-04-20
发明人： Hongmei Xie , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Alex Tang , Leonid Baryudin , Erich Franz Haratsch
IPC分类号： G06F3/06
摘要： A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.
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公开(公告)号：US10177787B1
公开(公告)日：2019-01-08
申请号：US14856674
申请日：2015-09-17
发明人： Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
摘要： An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.
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公开(公告)号：US11042316B1
公开(公告)日：2021-06-22
申请号：US16564866
申请日：2019-09-09
发明人： Hongmei Xie , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Alex Tang , Leonid Baryudin , Erich Franz Haratsch
IPC分类号： G06F3/06
摘要： A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.
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公开(公告)号：US10666295B1
公开(公告)日：2020-05-26
申请号：US16225272
申请日：2018-12-19
发明人： Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
摘要： An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.
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公开(公告)号：US10263640B2
公开(公告)日：2019-04-16
申请号：US15478895
申请日：2017-04-04
发明人： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC分类号： H03M13/11
摘要： Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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公开(公告)号：US11139833B2
公开(公告)日：2021-10-05
申请号：US16589564
申请日：2019-10-01
摘要： Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).
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公开(公告)号：US20190354498A1
公开(公告)日：2019-11-21
申请号：US15982210
申请日：2018-05-17
发明人： David Scott Ebsen , Dana Lynn Simonson , AbdelHakim Alhussien , Erich Franz Haratsch , Steven Howe
摘要： A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.
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