公开(公告)号：US08791734B1

公开(公告)日：2014-07-29

申请号：US13766035

申请日：2013-02-13

Applicant: Silicon Laboratories Inc.

Inventor： Susumu Hara ,  Adam D. Eldredge ,  Jeffrey S. Batchelor ,  Daniel Gallant

IPC: H03L7/06

CPC classification number: H03L7/235 ,  H03L7/146

Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Abstract translation: 级联锁相环（PLL）时钟产生技术降低了保持模式下低抖动时钟信号的频率漂移。 一种装置包括：第一PLL电路，被配置为基于第一时钟信号和第一分频值产生控制信号。 该装置包括：第二PLL电路，被配置为基于低抖动时钟信号和第二分频值产生第一时钟信号。 该装置包括第三PLL电路，其被配置为基于第一时钟信号，第三除法器值和第二时钟信号产生第二除法器值。 低抖动时钟信号可能具有比第二时钟信号更大的温度依赖性，并且第二时钟信号可能具有比低抖动时钟信号更高的抖动。