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公开(公告)号：US09780796B2
公开(公告)日：2017-10-03
申请号：US15271096
申请日：2016-09-20
发明人： Yu Kou
CPC分类号： H03L7/0807 , H03L7/091 , H03L7/093 , H03L7/146 , H03M1/0624 , H03M1/1215 , H04L7/0016 , H04L7/0062 , H04L7/0079 , H04L7/0331
摘要： A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.
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公开(公告)号：US20170163409A1
公开(公告)日：2017-06-08
申请号：US15346321
申请日：2016-11-08
申请人： FUJITSU LIMITED
发明人： HIRONOBU HONGOU
CPC分类号： H04L7/0331 , H03L7/085 , H03L7/093 , H03L7/0992 , H03L7/1075 , H03L7/113 , H03L7/146
摘要： There is provided a phase synchronization circuit including: a generation circuit to which an input clock signal is input, and configured to shift the input clock signal by intervals at which numbers of clocks of the input clock signal become equal so as to generate a plurality of pulse signals; a plurality of counter circuits each configured to measure pulse intervals of each of the plurality of pulse signals generated by the generation circuit, respectively; an average value calculation circuit configured to calculate an average value of measured values by the plurality of counter circuits; a frequency calculation circuit configured to calculate a frequency of the input clock signal from the average value calculated by the average value calculation circuit; and a phase locked loop (PLL) circuit configured to perform a phase synchronization processing on the input clock signal, based on the frequency calculated by the frequency calculation circuit.
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3.发明申请CLOCK CONDITIONER CIRCUITRY WITH IMPROVED HOLDOVER EXIT TRANSIENT PERFORMANCE 有权时钟控制器电路具有改进的持有退出瞬态性能公开(公告)号：US20160164532A1
公开(公告)日：2016-06-09
申请号：US14956667
申请日：2015-12-02
发明人： Benyong Zhang , Anjin Du , Junqiang Shi
摘要： Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation.
摘要翻译： 公开了一种诸如时钟调节器的电路，其提供了从保持操作退出的改进能力，最显着的是在时钟信号输入到时钟调节器的PLL显着不同相的情况下。 该电路利用PLL根据参考时钟和反馈时钟产生输出时钟。 在保持模式期间，PLL被解锁。 当参考时钟变为可用并且可以退出保持模式时，保持控制器发出触发对PLL的输入相位同步的复位信号。 复位信号使产生反馈时钟输入的反馈分频器组件复位其相位，并在重新启动之后至少调整其分频比至少第一分频周期，使其下一个上升沿与参考时钟相位对准。 一旦PLL相位检测器的两个输入相位对准，PLL将被重新使能，PLL平滑恢复正常工作。
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4.发明申请公开(公告)号：US20160065224A1
公开(公告)日：2016-03-03
申请号：US14566859
申请日：2014-12-11
CPC分类号： H03L7/093 , H03L7/0991 , H03L7/146 , H03M3/458
摘要： Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.
摘要翻译： 本公开的某些方面支持用于在锁相环（PLL）装置中快速频率调节和重新锁定的方法和装置。 本公开的方面提出了一种用于在用于产生周期性信号的PLL装置的开环控制（OLC）模式下操作的方法和装置。 在OLC模式期间，可以禁用与PLL器件的数字控制振荡器（DCO）连接的电路的时钟。 与DCO生成的周期信号相关联的PLL输出频率可以通过输入到DCO的数字控制字直接控制。
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5.发明授权公开(公告)号：US09258001B1
公开(公告)日：2016-02-09
申请号：US14016972
申请日：2013-09-03
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , Alvin C. Storvik
CPC分类号： H03L7/148 , H03L7/087 , H03L7/0891 , H03L7/093 , H03L7/103 , H03L7/105 , H03L7/1075 , H03L7/146 , H03L7/18 , H03L7/22 , H03L2207/06
摘要： An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.
摘要翻译： 锁相环（PLL）或锁频环（FLL）的振荡器可以包括两个输入。 两个输入可以包括第一模拟输入和第二数字输入。 第二数字输入可以接收设置振荡器的期望输出时钟频率的数字信号和/或指示振荡器输出的频率范围的近似频率。 第一模拟输入可以接收代表PLL或FLL的输出时钟频率的期望频率的电压，以从由第二数字输入设置的近似频率微调输出频率。 第一模拟输入可以从主时钟输入信号产生。 当主时钟输入信号消失时，即使没有主时钟输入信号，第二数字信号控制振荡器的输出频率，以允许PLL或FLL的冗余操作。
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公开(公告)号：US08803573B2
公开(公告)日：2014-08-12
申请号：US13647470
申请日：2012-10-09
申请人： LSI Corporation
IPC分类号： H03L7/06
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/1075 , H03L7/146 , H03L2207/06
摘要： In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.
摘要翻译： 在所描述的实施例中，用于SerDes设备的基于VCO的CDR包括相位检测器，响应于第一控制信号的VCO和第二控制信号，并产生输出信号;频率校准模块，被配置为通过以下步骤校准输出信号的频率 执行粗略校准和随后的精细校准，齿轮控制模块及时控制第一和第二控制信号的增益变化，以及通过由频率校准模块产生的精细校准值产生的查找表，其中编程 通过采用存储在查表中的精细校准值的计算电路来计算变速控制模块的可变增益，计算电路的计算调节换档增益，并且调整换档增益，并且调整总体CDR 增益超过VCO控制曲线。
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公开(公告)号：US20140016543A1
公开(公告)日：2014-01-16
申请号：US14007055
申请日：2011-11-08
申请人： Toshihide Kuwabara
发明人： Toshihide Kuwabara
IPC分类号： H04W56/00
CPC分类号： H04W56/0015 , G04R40/00 , H03L7/146 , H04J3/0688
摘要： A synchronization device has a normal-signal generator, a reference-signal generator, and a phase difference detector. The normal-signal generator generates a normal signal whose timing is synchronized with a time signal from a satellite. The reference-signal generator generates a reference signal whose timing is synchronized with a received signal. The phase difference detector detects the phase difference between the reference signal and the normal signal. The normal-signal generator then controls the normal signal on the basis of the phase difference when the time signal cannot be obtained.
摘要翻译： 同步装置具有正常信号发生器，参考信号发生器和相位差检测器。 正常信号发生器产生正时信号，其定时与来自卫星的时间信号同步。 参考信号发生器产生其定时与接收信号同步的参考信号。 相位差检测器检测参考信号和正常信号之间的相位差。 然后，当不能获得时间信号时，正常信号发生器基于相位差来控制正常信号。
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8.发明授权Method and apparatus for precise open loop tuning of reference frequency within a wireless device 有权无线设备内基准频率精确开环调谐的方法和装置公开(公告)号：US08477878B2
公开(公告)日：2013-07-02
申请号：US13615349
申请日：2012-09-13
CPC分类号： H03L7/146 , H03J7/00 , H04L27/0014 , H04L2027/0046 , H04L2027/0053 , H04L2027/0079
摘要： A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.
摘要翻译： 一种用于校正参考频率信号中的错误的无线设备的通信子系统。 通信子系统包括用于产生参考频率信号的频率发生器和闭环参考频率校正模块，其在通信子系统以闭环模式操作时产生用于校正参考频率信号的参考频率调整信号。 子系统进一步包括开环频率校正装置，其在闭环模式期间对参考频率调整信号进行采样，并且当通信子系统以除闭环模式之外的模式操作时，产生用于校正参考频率信号的频率校正信号。
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9.发明授权Apparatus and method to hold PLL output frequency when input clock is lost 有权输入时钟丢失时保持PLL输出频率的装置和方法公开(公告)号：US08446193B2
公开(公告)日：2013-05-21
申请号：US13099253
申请日：2011-05-02
IPC分类号： H03L7/06
CPC分类号： H03L7/146 , H03L2207/08
摘要： A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.
摘要翻译： 一种时钟调理电路，包括相位检测器电路，该相位检测器电路被配置为提供指示待调节的参考时钟与所产生的时钟之间的相位关系的模拟调谐信号。 受控振荡器被配置为产生所生成的时钟，所产生的时钟具有响应于施加到受控振荡器的控制信号输入的模拟调谐信号而可调节的输出频率。 当模式控制电路处于跟踪模式时，提供转换器电路以产生模拟调谐信号的数字表示。 在参考时钟丢失的情况下，模式控制电路切换到保持模式，以便基于在丢失参考时钟之前产生的数字表示，向控制信号输入提供模拟保持信号。
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公开(公告)号：US08188796B2
公开(公告)日：2012-05-29
申请号：US12838719
申请日：2010-07-19
申请人： Dan Zhu , Reuben Pascal Nelson , Timir Raithatha , Wyn Palmer , John Cavey , Ziwei Zheng
发明人： Dan Zhu , Reuben Pascal Nelson , Timir Raithatha , Wyn Palmer , John Cavey , Ziwei Zheng
CPC分类号： H03L7/0994 , H03L7/0992 , H03L7/146 , H03L7/18 , H03L7/23 , H03L2207/50
摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).
摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入，反馈信号的第二输入，DPFD产生表示参考输入时钟和反馈信号之间的差的输出。 缓冲器可以耦合到DPFD，用于随时间存储差分信号。 SDM可以具有耦合到缓冲器的控制输入。 加法器可以具有耦合到SDM的输入和整数控制字的源。 第一分频器可以具有用于接收外部时钟信号的输入和耦合到加法器的控制输入，DCO产生具有表示外部时钟信号的频率的平均频率的输出时钟信号除以（N + F / M ）。
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