Multi-stage sample and hold circuit
    1.
    发明授权
    Multi-stage sample and hold circuit 有权
    多级采样保持电路

    公开(公告)号:US09576679B2

    公开(公告)日:2017-02-21

    申请号:US14511085

    申请日:2014-10-09

    CPC classification number: G11C27/026 G11C27/02 G11C27/024

    Abstract: A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.

    Abstract translation: 电路可以包括被配置为提供输入信号的低精度采样的第一采样节点,被配置为存储输入信号的高精度采样的第二采样节点以及耦合在输入和第一采样节点之间的第一开关电路 。 电路还可以包括耦合在第一采样节点和第二采样节点之间的第二开关电路,并且被配置为限制可以对第二采样节点放电的漏电流。

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