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    PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESISTOR MEMORY ELEMENTS FOR IN-MEMORY PIPELINE PROCESSING
    1.
    发明公开
    PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESISTOR MEMORY ELEMENTS FOR IN-MEMORY PIPELINE PROCESSING 审中-公开

    公开(公告)号：US20240120001A1

    公开(公告)日：2024-04-11

    申请号：US18045524

    申请日：2022-10-11

    申请人： GlobalFoundries U.S. Inc.

    发明人： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC分类号： G11C13/00 ,  G11C11/16 ,  G11C27/02

    CPC分类号： G11C13/0026 ,  G11C11/1655 ,  G11C13/0004 ,  G11C13/0038 ,  G11C27/02

    摘要： A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

    Current-based track and hold circuit
    2.
    发明授权
    Current-based track and hold circuit 有权

    公开(公告)号：US11916567B2

    公开(公告)日：2024-02-27

    申请号：US17570658

    申请日：2022-01-07

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

    IPC分类号： H03M1/12 ,  G11C27/02

    CPC分类号： H03M1/1245 ,  G11C27/02 ,  H03M1/121

    摘要： An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

    SAMPLING CIRCUITRY WITH TEMPERATURE INSENSITIVE BANDWIDTH
    4.
    发明申请
    SAMPLING CIRCUITRY WITH TEMPERATURE INSENSITIVE BANDWIDTH 审中-公开

    公开(公告)号：US20190238125A1

    公开(公告)日：2019-08-01

    申请号：US16121449

    申请日：2018-09-04

    申请人： MACOM Technology Solutions Holding, Inc.

    发明人： Yanfei CHEN ,  Hiva HEDAYATI

    IPC分类号： H03K17/14 ,  G11C27/02

    CPC分类号： H03K17/145 ,  G11C27/02

    摘要： A sampling circuitry with a temperature insensitive bandwidth can include a temperature dependent current source, a source-follower amplifier, a storage element and a clocked transmission gate. The source-follower amplifier can be biased by the temperature dependent current source. The source-follower amplifier can be coupled to an input signal node, and the clocked transmission gate can be coupled to a clock signal. The clocked transmission gate can be coupled between an output of the source-follower amplifier and a combination of the storage element and an output signal node. A temperature-based variance in an output impedance of source-follower amplifier, an on-resistance of the clocked transmission gate and the capacitance of the storage element can be substantially cancelled by the temperature dependent current source.

    Top plate sampling circuit including input-dependent dual clock boost circuits
    6.
    发明授权
    Top plate sampling circuit including input-dependent dual clock boost circuits 有权

    公开(公告)号：US10084466B1

    公开(公告)日：2018-09-25

    申请号：US15856185

    申请日：2017-12-28

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

    IPC分类号： H03M1/10 ,  H03M1/12 ,  G06F1/04

    CPC分类号： H03M1/1245 ,  G06F1/04 ,  G11C27/02

    摘要： In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

    SAMPLE-AND-HOLD CIRCUIT FOR AN ELECTRICAL SIGNAL
    7.
    发明申请
    SAMPLE-AND-HOLD CIRCUIT FOR AN ELECTRICAL SIGNAL 审中-公开

    公开(公告)号：US20180197618A1

    公开(公告)日：2018-07-12

    申请号：US15866474

    申请日：2018-01-10

    申请人： Thales

    发明人： Arnaud Meyer ,  Bruno Louis ,  Rémi Corbiere ,  Vincent Petit ,  Patricia Desgreys ,  Hervé Petit

    IPC分类号： G11C27/02

    CPC分类号： G11C27/02 ,  H03M1/124 ,  H03M1/1245 ,  H03M9/00

    摘要： Sample-and-hold device for an electrical signal including an input module having two inputs, including a first switching block including two input switches, each input of the input module being connected at the input of one of the input switches, the input module being connected at the input of a first track-and-hold module with two inputs and two outputs, so as to alternately convey the signal from one of the two inputs to one of the two inputs of the first track-and-hold module; the device including a second track-and-hold module connected in parallel with the first track-and-hold module, these track-and-hold modules connected at the output of the first switching block, and an output module including a second switching block including two output switches, the outputs of the first and second track-and-hold modules being connected to the inputs of the output switches, to time interleave the output signals of the track-and-hold modules.

    State machine controlled MOS linear resistor
    8.
    发明授权
    State machine controlled MOS linear resistor 有权

    公开(公告)号：US10008283B2

    公开(公告)日：2018-06-26

    申请号：US15630676

    申请日：2017-06-22

    申请人： Sony Semiconductor Solutions Corporation

    发明人： Noam Eshel ,  Amit Sokolover ,  Golan Zeituni

    IPC分类号： G11C27/02 ,  H03K17/687

    CPC分类号： G11C27/02 ,  G11C27/024 ,  H03K17/687 ,  H04N5/378

    摘要： A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.