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公开(公告)号：US11843379B2
公开(公告)日：2023-12-12
申请号：US18092908
申请日：2023-01-03
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
CPC classification number: H03K21/026 , G06F1/3275 , H03K5/00006 , H03K21/10 , H03K21/406
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US11687432B2
公开(公告)日：2023-06-27
申请号：US17149663
申请日：2021-01-14
Applicant: Silicon Motion, Inc.
Inventor： Chun-Cheng Lee , Che-Min Lin , Kuan-Chun Yu , Sheng-I Hsu
CPC classification number: G06F11/3058 , G06F11/002 , G06F11/076 , G06F11/3037 , G06F12/0238 , G06F13/1668
Abstract: A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.
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公开(公告)号：US20220222160A1
公开(公告)日：2022-07-14
申请号：US17149663
申请日：2021-01-14
Applicant: Silicon Motion, Inc.
Inventor： Chun-Cheng Lee , Che-Min Lin , Kuan-Chun Yu , Sheng-I Hsu
Abstract: A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.
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公开(公告)号：US12160239B2
公开(公告)日：2024-12-03
申请号：US18498054
申请日：2023-10-31
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US20250055463A1
公开(公告)日：2025-02-13
申请号：US18928216
申请日：2024-10-28
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
IPC: H03K21/02 , G06F1/3234 , H03K5/00 , H03K21/10 , H03K21/40
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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Patent Agency Ranking
公开(公告)号：US11705907B2
公开(公告)日：2023-07-18
申请号：US17707992
申请日：2022-03-30
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
CPC classification number: H03K21/026 , G06F1/3275 , H03K5/00006 , H03K21/10 , H03K21/406
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US20230141572A1
公开(公告)日：2023-05-11
申请号：US18092908
申请日：2023-01-03
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
IPC: H03K21/02 , H03K21/10 , G06F1/3234 , H03K5/00 , H03K21/40
CPC classification number: H03K21/026 , H03K21/10 , G06F1/3275 , H03K5/00006 , H03K21/406
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US11323122B2
公开(公告)日：2022-05-03
申请号：US17331577
申请日：2021-05-26
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.
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公开(公告)号：US20240080030A1
公开(公告)日：2024-03-07
申请号：US18498054
申请日：2023-10-31
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-l Hsu
IPC: H03K21/02 , G06F1/3234 , H03K5/00 , H03K21/10 , H03K21/40
CPC classification number: H03K21/026 , G06F1/3275 , H03K5/00006 , H03K21/10 , H03K21/406
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US20220224339A1
公开(公告)日：2022-07-14
申请号：US17707992
申请日：2022-03-30
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
IPC: H03K21/02 , H03K21/10 , G06F1/3234 , H03K5/00 , H03K21/40
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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