公开(公告)号：US11899945B2

公开(公告)日：2024-02-13

申请号：US17705413

申请日：2022-03-28

Applicant: Silicon Motion, Inc.

Inventor： Hong-Ren Fang ,  Chun-Che Yang ,  Cheng-Yu Lee ,  Te-Kai Wang

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method for performing communications specification version control of a memory device in predetermined communications architecture with aid of compatibility management, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to execute a device-side compatibility management procedure of a compatibility management function to detect whether the host device conforms to any version of multiple predetermined versions of a predetermined communications specification according to the first command to generate a detection result, and selectively switch from one firmware version to another firmware version according to the detection result; and utilizing the memory controller to send a first response to the host device through the transmission interface circuit, wherein the first response is sent to the host device in response to the first command.

公开(公告)号：US20240220159A1

公开(公告)日：2024-07-04

申请号：US18092451

申请日：2023-01-03

Applicant: Silicon Motion, Inc.

Inventor： Hong-Ren Fang ,  Guo-Jhang Hong ,  Lu-Ting Wu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0679

Abstract: A method for performing configuration management of a memory device in predetermined communications architecture with aid of electronic fuse (eFuse) data preparation, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to execute at least one procedure regarding MP initialization of the memory device, for example, operations of a first procedure among the at least one procedure may include obtaining eFuse information from an eFuse circuit, preparing protected eFuse data according to the eFuse information, and storing the protected eFuse data into a non-volatile (NV) memory; and utilizing the memory controller to send a first response to the host device through the transmission interface circuit, wherein the first response is sent to the host device in response to the first command.

公开(公告)号：US20240028508A1

公开(公告)日：2024-01-25

申请号：US18213899

申请日：2023-06-26

Applicant: Silicon Motion, Inc.

Inventor： Hong-Ren Fang ,  Hao-Hsuan Wang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

公开(公告)号：US12222856B2

公开(公告)日：2025-02-11

申请号：US18213899

申请日：2023-06-26

Applicant: Silicon Motion, Inc.

Inventor： Hong-Ren Fang ,  Hao-Hsuan Wang

IPC: G06F12/02

Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

公开(公告)号：US20240377989A1

公开(公告)日：2024-11-14

申请号：US18623061

申请日：2024-04-01

Applicant: Silicon Motion, Inc.

Inventor： Ming-Yu Tsai ,  Hong-Ren Fang ,  Hsin-Ying Teng ,  Shih-Min Yen

IPC: G06F3/06

Abstract: The present invention provides a flash memory controller configured to access a flash memory module. The flash memory controller includes a transmission interface circuit, a buffer memory and a microprocessor. The transmission interface circuit is coupled to a host device, and the transmission interface circuit includes a time queue, at least one virtual queue and a command processing circuit, wherein the command processing circuit is configured to receive a plurality commands from a host device, write information of the plurality of commands into the time queue in sequence, and write the information of at least part of the plurality of commands into the at least one virtual queue. The buffer memory is configured to store the plurality of commands. The microprocessor is configured to selectively read the time queue or the at least one virtual queue to read the information of the plurality of commands.

公开(公告)号：US12026403B1

公开(公告)日：2024-07-02

申请号：US18092451

申请日：2023-01-03

Applicant: Silicon Motion, Inc.

Inventor： Hong-Ren Fang ,  Guo-Jhang Hong ,  Lu-Ting Wu

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0679

Abstract: A method for performing configuration management of a memory device in predetermined communications architecture with aid of electronic fuse (eFuse) data preparation, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to execute at least one procedure regarding MP initialization of the memory device, for example, operations of a first procedure among the at least one procedure may include obtaining eFuse information from an eFuse circuit, preparing protected eFuse data according to the eFuse information, and storing the protected eFuse data into a non-volatile (NV) memory; and utilizing the memory controller to send a first response to the host device through the transmission interface circuit, wherein the first response is sent to the host device in response to the first command.