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公开(公告)号：US11995349B2
公开(公告)日：2024-05-28
申请号：US17959308
申请日：2022-10-04
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
IPC: G06F3/06
CPC classification number: G06F3/0658 , G06F3/0607 , G06F3/0679
Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.
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公开(公告)号：US11249685B2
公开(公告)日：2022-02-15
申请号：US16888863
申请日：2020-06-01
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each clock includes a plurality of pages, and the method includes the steps of: providing a read-retry table, wherein the read-retry table includes a plurality of read setting levels, each read setting level corresponds to at least one read voltage, and no two read setting levels have the same read voltage; establishing a read success recording table, which records at least one specific read setting level that was previously used to successfully read the flash memory module; and when it is required to the read the flash memory module, using the at least one specific read setting level recorded in the read success recording table to read the flash memory module.
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公开(公告)号：US20240111451A1
公开(公告)日：2024-04-04
申请号：US17959308
申请日：2022-10-04
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
IPC: G06F3/06
CPC classification number: G06F3/0658 , G06F3/0607 , G06F3/0679
Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.
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公开(公告)号：US10048870B2
公开(公告)日：2018-08-14
申请号：US15844890
申请日：2017-12-18
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai Cheng , Yu-Chih Lin
Abstract: In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.
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公开(公告)号：US09329992B2
公开(公告)日：2016-05-03
申请号：US14096740
申请日：2013-12-04
Applicant: Silicon Motion, Inc.
Inventor： Chia-Chien Wu , Yu-Chih Lin , Yen-Hung Lin
CPC classification number: G06F12/0246 , G06F11/073 , G06F11/079 , G06F12/1441 , G06F21/00 , G06F2212/1052 , G06F2212/7202
Abstract: A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs two pages into the at least one replay-protected memory block and each page is programmed with a write count of the at least one replay-protected memory block.
Abstract translation: 一种使用具有重放保护块的闪存的数据存储设备。 FLASH存储器的存储空间被划分为块，每个块进一步分为页。 在数据存储设备中提供控制器以耦合到闪速存储器。 控制器管理闪存的至少一个重放保护的存储器块。 控制器将两个页面编程到至少一个重放保护的存储器块中，并且每个页面被编程为至少一个重放保护的存储器块的写入计数。
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Patent Agency Ranking
公开(公告)号：US11630602B2
公开(公告)日：2023-04-18
申请号：US17576998
申请日：2022-01-16
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
IPC: G06F3/06
Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
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公开(公告)号：US20220137871A1
公开(公告)日：2022-05-05
申请号：US17576998
申请日：2022-01-16
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
IPC: G06F3/06
Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
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公开(公告)号：US11262938B2
公开(公告)日：2022-03-01
申请号：US17082032
申请日：2020-10-28
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
IPC: G06F3/06
Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
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公开(公告)号：US20210294524A1
公开(公告)日：2021-09-23
申请号：US16888863
申请日：2020-06-01
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each clock includes a plurality of pages, and the method includes the steps of: providing a read-retry table, wherein the read-retry table includes a plurality of read setting levels, each read setting level corresponds to at least one read voltage, and no two read setting levels have the same read voltage; establishing a read success recording table, which records at least one specific read setting level that was previously used to successfully read the flash memory module; and when it is required to the read the flash memory module, using the at least one specific read setting level recorded in the read success recording table to read the flash memory module.
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公开(公告)号：US10275187B2
公开(公告)日：2019-04-30
申请号：US15246110
申请日：2016-08-24
Applicant: Silicon Motion, Inc.
Inventor： Yu-Chih Lin
Abstract: A memory device is provided. A processor accesses non-volatile memories via channels and generates a status table according to at least one command of a command queue. The status table records a plurality of tasks. Each task corresponds to one read status and one channel number. The processor selects a plurality of specific tasks from the tasks to serve as a first task set and simultaneously performs all the selected specific tasks with different channel numbers. When the read status of a first specific task matches a first predetermined status, the processor retrieves a logical-to-physical address mapping table relating to the logical address of the first specific task. When the read status of the first specific task matches a second predetermined status, the processor retrieves data relating to the logical address of the first specific task.
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