公开(公告)号：US09436599B2

公开(公告)日：2016-09-06

申请号：US14100575

申请日：2013-12-09

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng ,  Kuan-Yu Ke

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F2212/2022 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels. The control method further includes allocating the random access memory to provide a second set of cache spaces; and using the second set of cache spaces to perform data arrangement for the write data issued from the host when writing the data arranged in the first set of cache spaces for every channel to the FLASH memory.

Abstract translation: 公开了具有通过多个通道访问的FLASH存储器和FLASH存储器控制方法的数据存储装置。 所述控制方法包括将多个FLASH存储器块分成多个通道分别访问的组，每个块包括多个页面; 分配随机存取存储器以为所述多个通道中的不同通道提供第一组高速缓存空间; 将从主机发出的对应于所述多个信道的写入数据分离; 并且在每个通道的第一组高速缓存空间中的数据排列完成之后，经由多个通道将布置在每个通道的第一组高速缓存空间中的数据写入FLASH存储器。 控制方法还包括分配随机存取存储器以提供第二组高速缓存空间; 以及使用所述第二组高速缓存空间来为每个频道将布置在第一组高速缓存空间中的数据写入到FLASH存储器时，对从主机发出的写入数据执行数据排列。

公开(公告)号：US09208074B2

公开(公告)日：2015-12-08

申请号：US14014941

申请日：2013-08-30

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2212/7201

Abstract: A mapping table H2F update technique for a FLASH memory is disclosed. In the disclosed data storage device, when a master buffer block selected from a plurality of blocks of a FLASH memory to buffer write data from a host is full, the controller updates a logical-to-physical address mapping table for the master buffer block in separated update sub-intervals. Between the separated update sub-intervals, the controller responds to commands from the host. In this manner, commands from the host are responded to in a timely manner, without being postponed by a time-consuming mapping-table update of an entire buffer block.

Abstract translation: 公开了一种用于FLASH存储器的映射表H2F更新技术。 在公开的数据存储装置中，当从多个FLASH存储器块中选择缓冲来自主机的写入数据的主缓冲器块满时，控制器更新主缓冲块的逻辑到物理地址映射表， 分隔更新子间隔。 在分离的更新子间隔之间，控制器响应来自主机的命令。 以这种方式，来自主机的命令被及时响应，而不会被整个缓冲块的耗时的映射表更新推迟。

公开(公告)号：US09013922B2

公开(公告)日：2015-04-21

申请号：US13966554

申请日：2013-08-14

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng

IPC: G11C16/16 ,  G06F12/06

CPC classification number: G11C16/16 ,  G06F12/0246 ,  G06F12/06 ,  G06F2212/1016 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: Storage space allocation and a wear leveling technique for a FLASH memory module are disclosed. The FLASH memory module includes a plurality of FLASH chips. A controller for the FLASH memory module divides the storage space of the FLASH memory module into Xblocks for management of the FLASH memory module. The controller erases at least one Xblock for space release and moves data on Xblocks for wear leveling.

Abstract translation: 公开了存储空间分配和用于闪速存储器模块的损耗均衡技术。 闪存模块包括多个闪存芯片。 用于FLASH存储器模块的控制器将FLASH存储器模块的存储空间划分为用于管理FLASH存储器模块的Xblock。 控制器至少擦除一个Xblock以释放空间，并移动Xblock上的数据进行磨损均衡。

公开(公告)号：US10048870B2

公开(公告)日：2018-08-14

申请号：US15844890

申请日：2017-12-18

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng ,  Yu-Chih Lin

IPC: G11C7/00 ,  G06F3/06

Abstract: In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.

公开(公告)号：US09563551B2

公开(公告)日：2017-02-07

申请号：US14302692

申请日：2014-06-12

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block.

Abstract translation: 提供数据存储装置。 耦合到主机的数据存储设备包括：闪速存储器; 以及控制器，被配置为控制所述闪存的访问; 其中当所述主机执行对所述闪速存储器的随机数据访问时，所述控制器基于全局映射表检索与要读取的第一数据相关联的所述闪速存储器中的相应块和对应页的地址信息，并且预取相应的 基于地址信息从闪存读取页面; 其中，当所述控制器获取所述地址信息时，所述控制器还基于本地映射表来确定所述第一数据是否位于当前缓冲块中; 其中，当所述第一数据位于所述当前缓冲块中时，所述控制器进一步取消所述预取的对应页面，并且从当前缓冲块读取所述第一数据。

公开(公告)号：US09244833B2

公开(公告)日：2016-01-26

申请号：US13862816

申请日：2013-04-15

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/1008 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7207

Abstract: FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table.

Abstract translation: FLASH存储器被分配以提供数据存储设备和管理表。 管理表可以以由至少两个级别组成的分级结构记录逻辑到物理地址映射信息。 此外，除了逻辑到物理地址映射信息之外，管理表还可以提供有效页计数表和无效块记录。 在有效页计数表的更新完成之后，逻辑到物理地址映射信息被更新。 无效块记录是基于有效的页面计数表来维护的。

公开(公告)号：US20190155507A1

公开(公告)日：2019-05-23

申请号：US15948997

申请日：2018-04-09

Applicant: Silicon Motion Inc.

Inventor： Chang-Kai Cheng ,  Shen-Ting Chiu ,  Jing-Yi Chen

IPC: G06F3/06 ,  G06F12/1009

Abstract: A method for performing system backup in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The memory device includes a non-volatile (NV) memory including at least one NV memory element. The method may include: writing system information of the memory device at a plurality of locations within the NV memory to make the system information be stored at a first location and a second location within the plurality of locations, respectively, wherein the system information is internal control information of the memory device, and the system information stored at the second location is equivalent to that stored at the first location; and when the system information stored at the first location is not available, reading the system information stored at the second location to control the memory device to operate according to the system information read from the second location.

公开(公告)号：US09875032B2

公开(公告)日：2018-01-23

申请号：US15618232

申请日：2017-06-09

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng ,  Yu-Chih Lin

IPC: G11C7/00 ,  G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00

Abstract: The present invention provides a data storage device including a flash memory, a controller and a delay circuit. The controller receives a read command from a host, reads a first data sector from the flash memory according to the read command, and produces a setting signal according to the maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit receives the setting signal from the controller, divides the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmits at least one of the first sub-data sectors to the host at a predetermined time interval for extending the busy time of the controller.

公开(公告)号：US09563550B2

公开(公告)日：2017-02-07

申请号：US13970779

申请日：2013-08-20

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G11C29/00 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C16/349 ,  G11C29/82

Abstract: A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged.

Abstract translation: FLASH存储器用于数据存储，并进一步存储有逻辑到物理地址映射表和写保护映射表。 写保护映射表显示不同逻辑地址的写保护状态。 根据通过来自主机的动态容量管理命令发出的逻辑地址，数据存储设备的控制器修改逻辑到物理地址映射表，以破坏所发布的逻辑地址的逻辑到物理映射关系。 此外，控制器在写保护映射表中将对应于发布的逻辑地址的标志置为写保护模式。 根据写保护映射表的写保护标志量的变化，控制器调整闪存存储器的寿命终止判定值，从而延长闪存的寿命。

公开(公告)号：US09355028B2

公开(公告)日：2016-05-31

申请号：US14851186

申请日：2015-09-11

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/1008 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7207

Abstract: A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided.

Abstract translation: 具有分配用于提供数据存储空间的闪速存储器，有效页计数表，逻辑到物理地址映射信息和无效块记录的数据存储设备。 数据存储装置还具有控制器，分配数据存储空间以存储从主机发出的数据，以及建立和维护有效页计数表，逻辑到物理地址映射信息和无效块记录 FLASH存储器来管理数据存储空间。 还提供了闪速存储器控制方法。