公开(公告)号：US10607703B2

公开(公告)日：2020-03-31

申请号：US16042000

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11521

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

公开(公告)号：US11315636B2

公开(公告)日：2022-04-26

申请号：US16784183

申请日：2020-02-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hsuan Liang ,  Man Tang Wu ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Lihsin Chang ,  Nhan Do

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H01L27/11521

Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.

公开(公告)号：US20190355424A1

公开(公告)日：2019-11-21

申请号：US16042000

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/16 ,  G11C16/04

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.