公开(公告)号：US20150067211A1

公开(公告)日：2015-03-05

申请号：US14452818

申请日：2014-08-06

Applicant: Sony Computer Entertainment Inc.

Inventor： Hidehiro Inooka ,  Yuta Wakasugi ,  Seiji Asano ,  Yuichi Inomata ,  Hirotoshi Tokumo ,  Michitoshi Kakuta ,  Masaki Minobe

IPC: G06F13/12 ,  G06F13/364

CPC classification number: G06F13/126 ,  G06F13/364 ,  Y02D10/14

Abstract: Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.

Abstract translation: 本发明公开了一种通过外围设备控制数据流的外围设备控制装置，所述外围设备控制装置包括：外围设备控制处理器，其可以控制一个或多个外围设备的操作; 以及适于连接外围设备控制处理器，主处理器和一个或多个外围设备的总线，主处理器设置在外围设备控制设备外部，以控制一个或多个外围设备的操作，其中 总线存储由主处理器和外围设备控制处理器参考的地址，以访问一个或多个外围设备，并且总线在主处理器处于活动状态时禁止外围设备控制处理器访问外围设备。

公开(公告)号：US09727495B2

公开(公告)日：2017-08-08

申请号：US14452818

申请日：2014-08-06

Applicant: Sony Computer Entertainment Inc.

Inventor： Hidehiro Inooka ,  Yuta Wakasugi ,  Seiji Asano ,  Yuichi Inomata ,  Hirotoshi Tokumo ,  Michitoshi Kakuta ,  Masaki Minobe

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/364

CPC classification number: G06F13/126 ,  G06F13/364 ,  Y02D10/14

Abstract: Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.