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    OVER-THE-AIR CALIBRATION OF ANTENNA SYSTEM
    3.
    发明申请
    OVER-THE-AIR CALIBRATION OF ANTENNA SYSTEM 有权

    公开(公告)号：US20220278760A1

    公开(公告)日：2022-09-01

    申请号：US17747895

    申请日：2022-05-18

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Masoud Kahrizi ,  Robert Baummer, JR. ,  Jean-Noel Rozec ,  Fabrice Jean André Belvèze ,  Paul Lee Pearson ,  Francois Lucien Emile Icher ,  Marc Gens ,  Pascal Triaire

    IPC: H04B17/11 ,  H04B1/38

    Abstract: In an embodiment, an apparatus includes a transmit section including a first baseband section and a first radio frequency (RF) section, wherein the transmit section is configured to receive a calibration signal, the first RF section is configured to generate a RF calibration signal based on modulating the calibration signal. The calibration signal comprises an orthogonal code based signal; and a receive section configured to receive the RF calibration signal over-the-air, the receive section includes a second RF section and a calibration section, the second RF section is configured to generate a received calibration signal based on the RF calibration signal, the received calibration signal and a reference signal associated with the RF calibration signal comprise inputs to the calibration section and the calibration section is configured to determine one or more of gain, baseband delay, or RF delay compensation values, based on the inputs, to calibrate the transmit section.

    PHASE LOCK LOOP (PLL) SYNCHRONIZATION
    4.
    发明申请
    PHASE LOCK LOOP (PLL) SYNCHRONIZATION 有权

    公开(公告)号：US20210376837A1

    公开(公告)日：2021-12-02

    申请号：US17401208

    申请日：2021-08-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

    IPC: H03L7/07 ,  H03L7/197

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

    Phase lock loop (PLL) synchronization
    10.
    发明授权
    Phase lock loop (PLL) synchronization 有权

    公开(公告)号：US11329653B2

    公开(公告)日：2022-05-10

    申请号：US17401208

    申请日：2021-08-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

    IPC: H03L7/07 ,  H03L7/197

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

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