-
公开(公告)号：US20070192752A1
公开(公告)日：2007-08-16
申请号：US11354425
申请日：2006-02-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.
摘要翻译： 提供了一种改进的设计电路解决方案。 从电路的设计中获得一组目标路径，每个目标路径具有旨在改进的性能属性。 获得对目标路径集中的一个或多个节点的影响。 选择一个或多个节点用于使用影响进行改进。 随后，提高了每个选定节点的性能属性。 例如，可以用具有改进的性能属性的实现来替换节点的实现。 可以获得替代实现提供的相对改进与对另一性能属性的相对损害，并用于选择节点以进行改进。 在一个实施例中，使用相对改进和影响来获得用于选择节点以进行改进的每个备选实现的灵敏度度量。 以这种方式，可以以更有效的方式改善电路。
-
公开(公告)号：US07500207B2
公开(公告)日：2009-03-03
申请号：US11354425
申请日：2006-02-15
申请人： Subhrajit Bhattacharya , Anthony Correale, Jr. , Nathaniel D. Hieter , Veena S. Pureswaran , Ruchir Puri
发明人： Subhrajit Bhattacharya , Anthony Correale, Jr. , Nathaniel D. Hieter , Veena S. Pureswaran , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.
摘要翻译： 提供了一种改进的设计电路解决方案。 从电路的设计中获得一组目标路径，每个目标路径具有旨在改进的性能属性。 获得对目标路径集中的一个或多个节点的影响。 选择一个或多个节点用于使用影响进行改进。 随后，提高了每个选定节点的性能属性。 例如，可以用具有改进的性能属性的实现来替换节点的实现。 可以获得替代实现提供的相对改进与对另一性能属性的相对损害，并用于选择节点以进行改进。 在一个实施例中，使用相对改进和影响来获得用于选择节点以进行改进的每个备选实现的灵敏度度量。 以这种方式，可以以更有效的方式改善电路。
-
公开(公告)号：US20060279334A1
公开(公告)日：2006-12-14
申请号：US11466754
申请日：2006-08-23
申请人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。
-
公开(公告)号：US07089510B2
公开(公告)日：2006-08-08
申请号：US10720562
申请日：2003-11-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
摘要翻译： 一种用于优化多电源集成电路中的电平转换器放置的方法和程序产品。 每个电平转换器被放置在最小功率点以最小化净功率和从第一（低）电压净源通过电平转换器到第二（较高）电压净接收器的过渡延迟。 然后，消除了低效率的电平转换器。 具有低于选定的最小锥度尺寸的扇形锥体的电平转换器被删除，并且删除的电平转换器的低电压源恢复。 接收来自多电平转换器的输入的更高电压电平的电路元件被等效的低电压电路元件代替。 低电压缓冲器驱动电平转换器都由单个所述电平转换器代替。
-
公开(公告)号：US20050114815A1
公开(公告)日：2005-05-26
申请号：US10720562
申请日：2003-11-24
申请人： Anthony Correale , David Kung , Douglass Lamb , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , David Kung , Douglass Lamb , Zhigang Pan , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
摘要翻译： 一种用于优化多电源集成电路中的电平转换器放置的方法和程序产品。 每个电平转换器被放置在最小功率点以最小化净功率和从第一（低）电压净源通过电平转换器到第二（较高）电压净接收器的过渡延迟。 然后，消除了低效率的电平转换器。 具有低于选定的最小锥度尺寸的扇形锥体的电平转换器被删除，并且删除的电平转换器的低电压源恢复。 接收来自多电平转换器的输入的更高电压电平的电路元件被等效的低电压电路元件代替。 低电压缓冲器驱动电平转换器都由单个所述电平转换器代替。
-
公开(公告)号：US20090032903A1
公开(公告)日：2009-02-05
申请号：US12251195
申请日：2008-10-14
申请人： Anthony Correale, JR. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
发明人： Anthony Correale, JR. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
IPC分类号： H01L29/00
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78 , H01L27/118
摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
摘要翻译： 一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。 电路行可以包括由低电压（Vdd1）电源供电的低压岛和由高电压（Vddh）电源供电的高压岛。 包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。 电平转换器可以放置高压电路元件。
-
公开(公告)号：US20050110519A1
公开(公告)日：2005-05-26
申请号：US10720466
申请日：2003-11-24
申请人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
IPC分类号： H03K19/0185 , H03K19/0948 , H03K19/094
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。
-
公开(公告)号：US07336100B2
公开(公告)日：2008-02-26
申请号：US11466754
申请日：2006-08-23
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。
-
公开(公告)号：US20070028193A1
公开(公告)日：2007-02-01
申请号：US11460537
申请日：2006-07-27
申请人： Anthony Correale , David Kung , Douglass Lamb , Zhigang Pan , Ruchir Puri , David Wallach
发明人： Anthony Correale , David Kung , Douglass Lamb , Zhigang Pan , Ruchir Puri , David Wallach
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78 , H01L27/118
摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
摘要翻译： 一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。 电路行可以包括由低电压（Vdd）电源供电的低压岛和由高电压（Vdd）供电供电的高电压岛。 包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。 电平转换器可以放置高压电路元件。
-
公开(公告)号：US07119578B2
公开(公告)日：2006-10-10
申请号：US10720466
申请日：2003-11-24
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。
-
-
-
-
-
-
-
-
-
搜索结果
73 条记录 (耗时 0.021 秒)
