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公开(公告)号：US07500207B2
公开(公告)日：2009-03-03
申请号：US11354425
申请日：2006-02-15
申请人： Subhrajit Bhattacharya , Anthony Correale, Jr. , Nathaniel D. Hieter , Veena S. Pureswaran , Ruchir Puri
发明人： Subhrajit Bhattacharya , Anthony Correale, Jr. , Nathaniel D. Hieter , Veena S. Pureswaran , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.
摘要翻译： 提供了一种改进的设计电路解决方案。 从电路的设计中获得一组目标路径，每个目标路径具有旨在改进的性能属性。 获得对目标路径集中的一个或多个节点的影响。 选择一个或多个节点用于使用影响进行改进。 随后，提高了每个选定节点的性能属性。 例如，可以用具有改进的性能属性的实现来替换节点的实现。 可以获得替代实现提供的相对改进与对另一性能属性的相对损害，并用于选择节点以进行改进。 在一个实施例中，使用相对改进和影响来获得用于选择节点以进行改进的每个备选实现的灵敏度度量。 以这种方式，可以以更有效的方式改善电路。
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2.发明授权Method for enabling multiple incompatible or costly timing environment for efficient timing closure 有权用于实现多个不兼容或昂贵的定时环境以实现有效的定时关闭的方法公开(公告)号：US08302049B2
公开(公告)日：2012-10-30
申请号：US12958431
申请日：2010-12-02
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
摘要翻译： 基于松弛值执行静态时序分析以验证和优化逻辑设计的方法包括：在所述逻辑设计内选择具有至少两个输入的已知值的一个或多个电路; 识别从所述已知值的输入中控制所选择的电路的输出到达时间的关键输入; 基于关键和非关键输入的到达时间之间的差异，确定电路的一个或多个非关键输入所需的到达时间; 并且基于关键和非关键输入的AT之间的差异来计算关键输入上的松弛。 基于由到达时间差定义的松弛的设计优化优选地使用反向合并边缘设计度量。 该度量确定时钟整形电路的非关键信号的输入到达时间的确切需要量的改善。
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3.发明授权公开(公告)号：US08234612B2
公开(公告)日：2012-07-31
申请号：US12862949
申请日：2010-08-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译： 通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元 具有最高备用利用率的区域。 使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。 由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。 备用单元插入具有最多边缘的区域（边缘可以加权）。 该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。
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4.发明申请CONE-AWARE SPARE CELL PLACEMENT USING HYPERGRAPH CONNECTIVITY ANALYSIS 有权使用HYPERGRAPH连接分析的CONE-AWARE SPARE CELL PLACEMENT公开(公告)号：US20120054707A1
公开(公告)日：2012-03-01
申请号：US12862949
申请日：2010-08-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译： 通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元 具有最高备用利用率的区域。 使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。 由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。 备用单元插入具有最多边缘的区域（边缘可以加权）。 该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。
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5.发明申请Method for Enabling Multiple Incompatible or Costly Timing Environments for Efficient Timing Closure 有权启用多个不兼容或成本高的定时环境以实现高效定时关闭的方法公开(公告)号：US20120144357A1
公开(公告)日：2012-06-07
申请号：US12958431
申请日：2010-12-02
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
摘要翻译： 基于松弛值执行静态时序分析以验证和优化逻辑设计的方法包括：在所述逻辑设计内选择具有至少两个输入的已知值的一个或多个电路; 识别从所述已知值的输入中控制所选择的电路的输出到达时间的关键输入; 基于关键和非关键输入的到达时间之间的差异，确定电路的一个或多个非关键输入的所需到达时间; 并且基于关键和非关键输入的AT之间的差异来计算关键输入上的松弛。 基于由到达时间差定义的松弛的设计优化优选地使用反向合并边缘设计度量。 该度量确定时钟整形电路的非关键信号的输入到达时间的确切需要量的改善。
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