公开(公告)号：US20140187022A1

公开(公告)日：2014-07-03

申请号：US14142553

申请日：2013-12-27

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  John A. Pitney ,  Peter D. Albrecht

IPC: H01L21/322 ,  H01L21/302

CPC classification number: H01L21/322 ,  C30B25/12 ,  H01L21/302 ,  H01L21/68735 ,  H01L21/6875

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract translation: 公开了用于制备具有减小的应变的异质结构的装置和方法。 异质结构可以包括符合具有与结构不同的晶格的表面层的半导体结构，以形成相对低缺陷的异质结构。

公开(公告)号：US20140182788A1

公开(公告)日：2014-07-03

申请号：US14142559

申请日：2013-12-27

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  John A. Pitney ,  Peter D. Albrecht

IPC: H01L21/67

CPC classification number: H01L21/322 ,  C30B25/12 ,  H01L21/302 ,  H01L21/67092 ,  H01L21/6838 ,  H01L21/68735 ,  H01L21/6875

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract translation: 用于制备具有降低的缺陷浓度的异质结构的装置，包括用于对半导体衬底施加应力以使其符合具有不同晶格常数的晶体的装置。

公开(公告)号：US20140187023A1

公开(公告)日：2014-07-03

申请号：US14142556

申请日：2013-12-27

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  John A. Pitney ,  Peter D. Albrecht

IPC: H01L21/322

CPC classification number: H01L21/322 ,  C30B25/12 ,  H01L21/302 ,  H01L21/68735 ,  H01L21/6875

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract translation: 公开了用于制备具有减小的应变的异质结构的装置和方法。 异质结构可以包括符合具有与结构不同的晶格的表面层的半导体结构，以形成相对低缺陷的异质结构。

公开(公告)号：US20140170781A1

公开(公告)日：2014-06-19

申请号：US14107806

申请日：2013-12-16

Applicant: SunEdison, Inc.

Inventor： Peter D. Albrecht ,  Sumeet S. Bhagavat

IPC: B24B7/22 ,  H01L21/66 ,  H01L21/306

CPC classification number: B24B7/228 ,  B24B37/08 ,  B24B37/12 ,  H01L21/30625 ,  H01L22/12

Abstract: A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate.

Abstract translation: 用于抛光晶片表面的压板具有反应板，抛光板和气囊。 反应板具有顶部和底部表面，并且限定纵向轴线。 抛光板与反应板同轴设置。 抛光板具有第二顶表面和第二底表面。 第二顶表面邻近反应板的底表面。 气囊沿着反应板的顶表面或底表面的径向外部同轴地定位。 气囊与抛光板连接，能够使抛光板相对于反应板的底面膨胀而变形。