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公开(公告)号：US11914545B2
公开(公告)日：2024-02-27
申请号：US17564487
申请日：2021-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC: G06F13/42 , G06F13/28 , H04L67/303
CPC classification number: G06F13/4234 , G06F13/28 , H04L67/303
Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
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Patent Agency Ranking
公开(公告)号：US10452594B2
公开(公告)日：2019-10-22
申请号：US14887885
申请日：2015-10-20
Applicant: Texas Instruments Incorporated
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
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公开(公告)号：US11243903B2
公开(公告)日：2022-02-08
申请号：US16658928
申请日：2019-10-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
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公开(公告)号：US20170109054A1
公开(公告)日：2017-04-20
申请号：US14887885
申请日：2015-10-20
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: G06F13/4234 , G06F13/28 , H04L67/303
Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
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公开(公告)号：US09454437B2
公开(公告)日：2016-09-27
申请号：US14309362
申请日：2014-06-19
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。
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公开(公告)号：US20150089293A1
公开(公告)日：2015-03-26
申请号：US14309362
申请日：2014-06-19
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。
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