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    COMPUTE THROUGH POWER LOSS HARDWARE APPROACH FOR PROCESSING DEVICE HAVING NONVOLATILE LOGIC MEMORY
    2.
    发明申请
    COMPUTE THROUGH POWER LOSS HARDWARE APPROACH FOR PROCESSING DEVICE HAVING NONVOLATILE LOGIC MEMORY 有权

    公开(公告)号：US20210373647A1

    公开(公告)日：2021-12-02

    申请号：US17404125

    申请日：2021-08-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

    Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

    DUAL-PORT NEGATIVE LEVEL SENSITIVE DATA RETENTION LATCH
    6.
    发明申请
    DUAL-PORT NEGATIVE LEVEL SENSITIVE DATA RETENTION LATCH 有权
    双端口负值敏感数据保持锁

    公开(公告)号：US20150061739A1

    公开(公告)日：2015-03-05

    申请号：US14311752

    申请日：2014-06-23

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: H03K3/356

    CPC classification number: H03K3/356008

    Abstract: In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

    Abstract translation: 在本发明的一个实施例中，双端口负电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和控制信号SS和SSN。 信号CKT，CLKZ，RET，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

    NEGATIVE EDGE RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
    7.
    发明申请
    NEGATIVE EDGE RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH 有权
    负边缘复位翻转双重端口从动锁

    公开(公告)号：US20140232442A1

    公开(公告)日：2014-08-21

    申请号：US14154458

    申请日：2014-01-14

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Bartling ,  Sudhanshu Khanna

    IPC: H03K3/3562

    CPC classification number: H03K3/35625 ,  H03K3/3562

    Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

    Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SS，RE和REN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

    POSITIVE EDGE PRESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
    8.
    发明申请
    POSITIVE EDGE PRESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH 有权
    积极边缘预置旋转双口双向锁

    公开(公告)号：US20140232441A1

    公开(公告)日：2014-08-21

    申请号：US13948901

    申请日：2013-07-23

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Bartling ,  Sudhanshu Khanna

    IPC: H03K3/037

    CPC classification number: H03K3/35625

    Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

    Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

    Four capacitor nonvolatile bit cell
    9.
    发明授权
    Four capacitor nonvolatile bit cell 有权
    四个电容器非易失性位单元

    公开(公告)号：US08797783B1

    公开(公告)日：2014-08-05

    申请号：US13753782

    申请日：2013-01-30

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C11/00 ,  G11C11/22

    CPC classification number: G11C11/221

    Abstract: A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.

    Abstract translation: 片上系统（SoC）提供了非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 钳位电路耦合到节点Q并且可操作以在不访问位单元的情况下将节点Q钳位到大致等于第一电压的电压。

    Nonvolatile logic array with built-in test drivers
    10.
    发明授权
    Nonvolatile logic array with built-in test drivers 有权
    具有内置测试驱动器的非易失逻辑阵列

    公开(公告)号：US08792288B1

    公开(公告)日：2014-07-29

    申请号：US13753800

    申请日：2013-01-30

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C7/22 ,  G11C29/08

    CPC classification number: G11C29/36 ,  G11C7/12 ,  G11C7/20 ,  G11C11/419 ,  G11C2029/1204

    Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

    Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个m个驱动器都耦合到m个位线中的对应的一个，其中m个驱动器各自包括写入一个电路和写入零电路。 响应于耦合到写入一个电路的第一控制信号并且响应于耦合到写入的第二控制信号将全零写入位单元行中，m个驱动器可操作以将所有的一个写入一行位单元 零电路。

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