公开(公告)号：US20210265985A1

公开(公告)日：2021-08-26

申请号：US17319505

申请日：2021-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan SUBBANNAVAR ,  Arnab KHAWAS ,  Suvam NANDI

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US20210184659A1

公开(公告)日：2021-06-17

申请号：US16713343

申请日：2019-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan SUBBANNAVAR ,  Arnab KHAWAS ,  Suvam NANDI

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.