公开(公告)号：US20210265985A1

公开(公告)日：2021-08-26

申请号：US17319505

申请日：2021-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan SUBBANNAVAR ,  Arnab KHAWAS ,  Suvam NANDI

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US20230135349A1

公开(公告)日：2023-05-04

申请号：US17514856

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Rakesh DIMRI ,  Badarish Mohan SUBBANNAVAR ,  Somasekar J.

IPC: H01L27/118

Abstract: An IC includes first-third power rails. The first-third power rails are located along corresponding first-third centerlines spaced apart by the same distance. A plurality of first logic cells is in first and second width that is an integer multiple of a unit width and a first semiconductor structure that includes multiple transistors. For each first logic cell in the first row, the first semiconductor structure is located entirely between the first and second centerlines. For each first logic cell in the second row, the first semiconductor structure is located entirely between the first and third centerlines. A multi-height logic cell includes a second height that is greater than the first height, and a second width that is at least the unit width. The second semiconductor structure includes at least two transistors. The second semiconductor structure is partially between the first and second centerlines and between the first and third centerlines.

公开(公告)号：US20170194943A1

公开(公告)日：2017-07-06

申请号：US15391465

申请日：2016-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam NANDI ,  Badarish Mohan SUBBANNAVAR

IPC: H03K3/012 ,  H03K19/00 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625 ,  H03K19/0002 ,  H03K19/09429

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

公开(公告)号：US20230140528A1

公开(公告)日：2023-05-04

申请号：US17514580

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Rakesh DIMRI ,  Badarish Mohan SUBBANNAVAR ,  Somasekar J

IPC: H01L27/118

Abstract: An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

公开(公告)号：US20210184659A1

公开(公告)日：2021-06-17

申请号：US16713343

申请日：2019-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan SUBBANNAVAR ,  Arnab KHAWAS ,  Suvam NANDI

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.