公开(公告)号：US20240372767A1

公开(公告)日：2024-11-07

申请号：US18399278

申请日：2023-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh BALAKRISHNAN ,  Aswath VS ,  Sriram MURALI ,  Sreenath NARAYANAN POTTY ,  Sundarrajan RANGACHARI ,  Girish NADIGER ,  Kapil KUMAR

IPC: H04L27/26

Abstract: Crest factor reduction circuitry includes: a peak neighborhood analyzer; peak detection circuitry and a controller. The peak neighborhood analyzer is configured to: receive an input signal; analyze the input signal to determine whether a peak larger than a target threshold is expected within an interval; and provide a first control signal responsive to determining that a peak larger than the target threshold is expected within the interval. The controller is configured to: receive the first control signal; and gate a clock or data to the peak detection circuitry responsive to the first control signal.

公开(公告)号：US20240364569A1

公开(公告)日：2024-10-31

申请号：US18632062

申请日：2024-04-10

Applicant: Texas Instruments Incorporated

Inventor： Raju Kharataram Chaudhari ,  Aswath VS ,  Sriram Murali ,  Jaiganesh Balakrishnan ,  Sreenath Narayanan Potty ,  Kapil Kumar

IPC: H04L27/26 ,  H04B1/04

CPC classification number: H04L27/2618 ,  H04B1/0475

Abstract: An example apparatus includes: crest factor reduction circuitry having a signal input and a peak cancellation waveform input; and peak cancellation waveform generator circuitry including: carrier profile analyzer circuitry having a signal input coupled to the signal input of the crest factor reduction circuitry, and having a carrier profile output; waveform construction circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, having a second input, and having a peak cancellation waveform output coupled to the peak cancellation waveform input of the crest factor reduction circuitry; and profile change detector circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, and having an output coupled to the second input of the waveform construction circuitry.

公开(公告)号：US20220173947A1

公开(公告)日：2022-06-02

申请号：US17538460

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh BALAKRISHNAN ,  Nagalinga Swamy Basayya AREMALLAPUR ,  Aswath VS

IPC: H04L27/14

Abstract: A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.

公开(公告)号：US20230387975A1

公开(公告)日：2023-11-30

申请号：US17829218

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Divyeshkumar Mahendrabhai PATEL ,  Sai Vaibhav BATCHU ,  Divyansh Deepak JAIN ,  Aswath VS

IPC: H04B7/06

CPC classification number: H04B7/06

Abstract: Examples of this description provide for a method. In some examples, the method includes determining, via a circuit, an estimated value of harmonic coupling in a transmitted signal via a feedback signal path that receives the transmitted signal and performing pre-compensation for the harmonic coupling based on the estimated value, the pre-compensation performed in the circuit.

公开(公告)号：US20230275594A1

公开(公告)日：2023-08-31

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US20250047531A1

公开(公告)日：2025-02-06

申请号：US18651130

申请日：2024-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Aswath VS ,  Sriram Murali ,  Sreenath Narayanan Potty ,  Raju Kharataram Chaudhari ,  Kapil Kumar

IPC: H04L25/03 ,  H04L27/26

Abstract: An example apparatus described herein to implement cancellation pulse generation includes a first memory storing first subsets of data samples of a single pulse cancellation waveform. The example apparatus includes a second memory storing second subsets of data samples of the single pulse cancellation waveform, the second subsets including different data samples of the single pulse cancellation waveform than the first subsets. The example apparatus includes first circuitry coupled to the first memory and to the second memory in parallel. The example apparatus includes a plurality of buffers. The example apparatus includes second circuitry coupled to the plurality of buffers.

公开(公告)号：US20250039027A1

公开(公告)日：2025-01-30

申请号：US18638460

申请日：2024-04-17

Applicant: Texas Instruments Incorporated

Inventor： Sriram Murali ,  Aswath VS ,  Sreenath Narayanan Potty ,  Raju K. Chaudhari ,  Kapil Kumar

IPC: H04L27/26 ,  H04B1/04

Abstract: An example apparatus to reduce crests in an input signal includes: memory; and programmable circuitry configured to: store a first copy and a second copy of a normalized window waveform in the memory, the first copy of the normalized window waveform including more data points than the second copy of the normalized window waveform; use the second copy of the normalized window waveform to generate a weight corresponding to a peak in the input signal; use the weight and the first copy of the normalized window waveform to generate an output waveform; generate a peak limiting waveform responsive to the output waveform; and combine the peak limiting waveform with the input signal to reduce an amplitude of the peak.

公开(公告)号：US12057854B2

公开(公告)日：2024-08-06

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US20190207612A1

公开(公告)日：2019-07-04

申请号：US15949294

申请日：2018-04-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Sundarrajan RANGACHARI ,  Aswath VS ,  Raunak DHANIWALA

IPC: H03L7/24 ,  H03L7/02 ,  H03K21/38

CPC classification number: H03L7/24 ,  H03K21/38 ,  H03L7/02

Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.