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公开(公告)号：US20210119661A1
公开(公告)日：2021-04-22
申请号：US17072104
申请日：2020-10-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram MURALI , Jaiganesh BALAKRISHNAN , Pooja SUNDAR , Harshavardhan ADEPU , Wenjing LU , Yeswanth GUNTUPALLI
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US20220231667A1
公开(公告)日：2022-07-21
申请号：US17463317
申请日：2021-08-31
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh BALAKRISHNAN , Sriram MURALI , Kalyan GUDIPATI , Venkateshwara Reddy POTHAPU , Sarma Sundareswara GUNTURI
Abstract: Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.
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公开(公告)号：US20220029657A1
公开(公告)日：2022-01-27
申请号：US17493943
申请日：2021-10-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram MURALI , Jaiganesh BALAKRISHNAN , Pooja SUNDAR , Harshavardhan ADEPU , Wenjing LU , Yeswanth GUNTUPALLI
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US20200309939A1
公开(公告)日：2020-10-01
申请号：US16363719
申请日：2019-03-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik SUBBURAJ , Sandeep RAO , Sriram MURALI , Karthik RAMASUBRAMANIAN
Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.
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公开(公告)号：US20220116030A1
公开(公告)日：2022-04-14
申请号：US17558794
申请日：2021-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram MURALI , Jaiganesh BALAKRISHNAN , Ram Narayan KRISHNA NAMA MONY , Pooja SUNDAR
IPC: H03K5/1252 , G11C19/28 , G06F1/10 , G06F1/08 , H03K19/21
Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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Patent Agency Ranking
公开(公告)号：US20210075368A1
公开(公告)日：2021-03-11
申请号：US16953666
申请日：2020-11-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.
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公开(公告)号：US20200162083A1
公开(公告)日：2020-05-21
申请号：US16269473
申请日：2019-02-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sundarrajan RANGACHARI , Sriram MURALI , Sanjay PENNAM
Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.
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公开(公告)号：US20200228126A1
公开(公告)日：2020-07-16
申请号：US16837537
申请日：2020-04-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sundarrajan RANGACHARI , Sriram MURALI , Sanjay PENNAM
Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.
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公开(公告)号：US20200212844A1
公开(公告)日：2020-07-02
申请号：US16403777
申请日：2019-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.
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公开(公告)号：US20240372767A1
公开(公告)日：2024-11-07
申请号：US18399278
申请日：2023-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh BALAKRISHNAN , Aswath VS , Sriram MURALI , Sreenath NARAYANAN POTTY , Sundarrajan RANGACHARI , Girish NADIGER , Kapil KUMAR
IPC: H04L27/26
Abstract: Crest factor reduction circuitry includes: a peak neighborhood analyzer; peak detection circuitry and a controller. The peak neighborhood analyzer is configured to: receive an input signal; analyze the input signal to determine whether a peak larger than a target threshold is expected within an interval; and provide a first control signal responsive to determining that a peak larger than the target threshold is expected within the interval. The controller is configured to: receive the first control signal; and gate a clock or data to the peak detection circuitry responsive to the first control signal.
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