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    MEMORY COMPRESSION OPERABLE FOR NON-CONTIGUOUS WRITE/READ ADDRESSES
    1.
    发明申请
    MEMORY COMPRESSION OPERABLE FOR NON-CONTIGUOUS WRITE/READ ADDRESSES 有权

    公开(公告)号：US20180041222A1

    公开(公告)日：2018-02-08

    申请号：US15782052

    申请日：2017-10-12

    Applicant: Texas Instruments Incorporated

    Inventor： Sundarrajan RANGACHARI ,  Desmond Pravin Martin FERNANDES ,  Rakesh Channabasappa Yaraduyathinahalli

    IPC: H03M7/30

    CPC classification number: H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

    Abstract: Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.

    DITHERED M BY N CLOCK DIVIDERS
    3.
    发明申请
    DITHERED M BY N CLOCK DIVIDERS 有权

    公开(公告)号：US20200162083A1

    公开(公告)日：2020-05-21

    申请号：US16269473

    申请日：2019-02-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sundarrajan RANGACHARI ,  Sriram MURALI ,  Sanjay PENNAM

    IPC: H03L7/197 ,  G06F7/58 ,  H03K21/02 ,  H03K21/10 ,  H03K3/84

    Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

    DITHERED M BY N CLOCK DIVIDERS
    6.
    发明申请
    DITHERED M BY N CLOCK DIVIDERS 审中-公开

    公开(公告)号：US20200228126A1

    公开(公告)日：2020-07-16

    申请号：US16837537

    申请日：2020-04-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sundarrajan RANGACHARI ,  Sriram MURALI ,  Sanjay PENNAM

    IPC: H03L7/197 ,  G06F7/58 ,  H03K21/02 ,  H03K3/84 ,  H03K21/10

    Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

    MULTIPLIER-BASED PROGRAMMABLE FILTERS
    7.
    发明申请
    MULTIPLIER-BASED PROGRAMMABLE FILTERS 审中-公开

    公开(公告)号：US20190181842A1

    公开(公告)日：2019-06-13

    申请号：US15839265

    申请日：2017-12-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sundarrajan RANGACHARI ,  Jaiganesh BALAKRISHNAN ,  Jawaharlal TANGUDU ,  Srinivas Kumar Reddy NARU

    IPC: H03H17/02

    Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

    CLOCK PULSE GENERATOR
    9.
    发明申请
    CLOCK PULSE GENERATOR 有权

    公开(公告)号：US20200177170A1

    公开(公告)日：2020-06-04

    申请号：US16281622

    申请日：2019-02-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Gautam Sanjay KALE ,  Sundarrajan RANGACHARI ,  Nagalinga Swamy Basayya AREMALLAPUR

    IPC: H03K5/131 ,  H03K23/54

    Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.

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