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公开(公告)号：US20140198977A1
公开(公告)日：2014-07-17
申请号：US13848697
申请日：2013-03-21
Applicant: Texas Instruments Incorporated
Inventor： Rajesh Narasimha , Karthik Jayaraman Raghuram , Jesse Gregory Villarreal, JR. , Roman Joel Pacheco
CPC classification number: G06K9/6212 , G06T5/007 , G06T7/593 , G06T2207/20016 , G06T2207/20021
Abstract: A method for computation of a depth map for corresponding left and right two dimensional (2D) images of a stereo image is provided that includes determining a disparity range based on a disparity of at least one object in a scene of the left and right 2D images, performing color matching of the left and right 2D images, performing contrast and brightness matching of the left and right 2D images, and computing a disparity image for the left and right 2D images after the color matching and the contrast and brightness matching are performed, wherein the disparity range is used for correspondence matching of the left and right 2D images.
Abstract translation: 提供了一种用于计算立体图像的相应左和右二维（2D）图像的深度图的方法，其包括基于左右2D图像的场景中的至少一个对象的视差来确定视差范围 执行左右2D图像的颜色匹配，执行左右2D图像的对比度和亮度匹配，以及在进行颜色匹配和对比度和亮度匹配之后计算左右2D图像的视差图像， 其中，所述视差范围用于左右2D图像的对应匹配。
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公开(公告)号：US20220237137A1
公开(公告)日：2022-07-28
申请号：US17582992
申请日：2022-01-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lucas Weaver , Jesse Gregory Villarreal, JR.
Abstract: An example system includes a pipeline depth determination circuit and a buffer depth determination circuit. The pipeline depth determination circuit is configured to analyze input-output connections between a plurality of processing nodes specified to perform a processing task, and determine a pipeline depth of the processing task based on the input-output connections. The buffer depth determination circuit is configured to analyze the input-output connections between the plurality of processing nodes, and assign, based on the input-output connections, a depth value to each of a plurality of buffer memories configured to store output of a first of the processing nodes for input to a second of the processing nodes.
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Patent Agency Ranking
公开(公告)号：US20180197036A1
公开(公告)日：2018-07-12
申请号：US15853204
申请日：2017-12-22
Applicant: Texas Instruments Incorporated
Inventor： Jesse Gregory Villarreal, JR.
CPC classification number: G06K9/46 , G06K9/4609 , G06K9/4671 , G06K9/6228 , G06K9/6267
Abstract: Methods, apparatus, systems to perform distance-based feature suppression of features of an image in a feature list of the image are disclosed. A method includes accessing the feature list, comparing a selected feature in the feature list with features located within a first distance of the selected feature, when features located within the first distance are non-suppressed or valid and are stronger than different non-suppressed features, marking the features as valid and marking other non-suppressed features as suppressed. When the features are suppressed or invalid and are not stronger than non-suppressed features, determining if features of the feature list are marked as valid or suppressed.
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公开(公告)号：US20210311782A1
公开(公告)日：2021-10-07
申请号：US17349310
申请日：2021-06-16
Applicant: Texas Instruments Incorporated
Inventor： Kedar Chitnis , Mihir Narendra Mody , Jesse Gregory Villarreal, JR. , Lucas Carl Weaver , Brijesh Jadav , Niraj Nandan
Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.
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公开(公告)号：US20250094221A1
公开(公告)日：2025-03-20
申请号：US18970449
申请日：2024-12-05
Applicant: Texas Instruments Incorporated
Inventor： Kedar Chitnis , Mihir Narendra Mody , Jesse Gregory Villarreal, JR. , Lucas Carl Weaver , Brijesh Jadav , Niraj Nandan
Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.
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公开(公告)号：US20200160103A1
公开(公告)日：2020-05-21
申请号：US16774185
申请日：2020-01-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jesse Gregory Villarreal, JR.
Abstract: Methods, apparatus, systems to perform distance-based feature suppression of features of an image in a feature list of the image are disclosed. A method includes accessing the feature list, comparing a selected feature in the feature list with features located within a first distance of the selected feature, when features located within the first distance are non-suppressed or valid and are stronger than different non-suppressed features, marking the features as valid and marking other non-suppressed features as suppressed. When the features are suppressed or invalid and are not stronger than non-suppressed features, determining if features of the feature list are marked as valid or suppressed.
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公开(公告)号：US20190286483A1
公开(公告)日：2019-09-19
申请号：US16298709
申请日：2019-03-11
Applicant: Texas Instruments Incorporated
Inventor： Kedar Chitnis , Mihir Narendra Mody , Jesse Gregory Villarreal, JR. , Lucas Carl Weaver , Brijesh Jadav , Niraj Nandan
Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.
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