FAULT TOLERANT DIGITAL INPUT RECEIVER CIRCUIT

    公开(公告)号:US20200182965A1

    公开(公告)日:2020-06-11

    申请号:US16411285

    申请日:2019-05-14

    Abstract: A digital input receiver system comprises a first input receiver having a first current limiter input, and a first voltage comparator input coupled to a first node. A first resistor is coupled between the first node and the first current limiter input. The first input receiver outputs a digital logic signal and is coupled to a second node. The receiver system further comprises a second input receiver having a second current limiter input, and a second voltage comparator input coupled to the second node. A second resistor is coupled between the second node and the second current limiter input. The second input receiver outputs a malfunction signal. The first and second input receivers are configured to limit current through the receiver system to less than an overcurrent threshold of the first and second input receivers.

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