公开(公告)号：US20220391345A1

公开(公告)日：2022-12-08

申请号：US17341089

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar KAMATH ,  Rakesh HARIHARAN ,  Vivekkumar Ramanlal VADODARIYA ,  Soumi PAUL ,  Mayank GARG

IPC: G06F13/42 ,  G06F13/38 ,  G06F1/3215

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

公开(公告)号：US20240380397A1

公开(公告)日：2024-11-14

申请号：US18657273

申请日：2024-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanth MUDDA ,  Tarunvir SINGH ,  Anant Shankar KAMATH ,  Kumar Anurag SHRIVASTAVA

IPC: H03K17/51 ,  H03K19/20

Abstract: In some examples, a circuit includes a sink/source mode detector configured to compare a voltage provided at the first I/O terminal of the circuit to a first reference signal; determine, responsive to the voltage provided at the first I/O terminal exceeding the first reference signal, that the circuit is in a source mode; determine, responsive to the voltage provided at the first I/O terminal not exceeding the first reference signal, that the circuit is in a sink mode; responsive to determining that the circuit is in the source mode and an input signal of the circuit has a value less than a second reference signal, control a first switch to form a first current path between a voltage supply terminal and the first I/O terminal of the circuit; and responsive to determining that the circuit is in the sink mode and the input signal has a value greater than the second reference signal, control a second switch to form a second current path between a ground terminal and the first I/O terminal of the circuit.

公开(公告)号：US20220107909A1

公开(公告)日：2022-04-07

申请号：US17244370

申请日：2021-04-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip BANERJEE ,  Sreeram Subramanyam NASUM ,  Anant Shankar KAMATH

IPC: G06F13/20 ,  H03K17/687 ,  G06F13/40

Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

公开(公告)号：US20230336083A1

公开(公告)日：2023-10-19

申请号：US17813366

申请日：2022-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dushmantha Bandara RAJAPAKSHA ,  Roland SPERLICH ,  Anant Shankar KAMATH ,  Vijayalakshmi DEVARAJAN ,  Wesley RAY

IPC: H02M3/335 ,  H01F27/28 ,  H04L13/02 ,  H02M3/155 ,  H02M1/42

CPC classification number: H02M3/33523 ,  H01F27/288 ,  H04L13/02 ,  H02M3/155 ,  H02M1/4258 ,  H02M3/33569 ,  H02M3/33573 ,  H02M3/01

Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

公开(公告)号：US20230412431A1

公开(公告)日：2023-12-21

申请号：US18241544

申请日：2023-09-01

Applicant: Texas Instruments Incorporated

Inventor： Sadia Arefin KHAN ,  Anant Shankar KAMATH ,  Martin STAEBLER ,  Vikas Kumar THAWANI

IPC: H04L25/02 ,  H02K11/33 ,  H03K19/0175 ,  H03K19/003 ,  H02P27/08

CPC classification number: H04L25/0266 ,  H02K11/33 ,  H03K19/017545 ,  H03K19/00323 ,  H03K19/017509 ,  H02P27/08

Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

公开(公告)号：US20200182965A1

公开(公告)日：2020-06-11

申请号：US16411285

申请日：2019-05-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kevin Paul HERRING ,  Anant Shankar KAMATH

IPC: G01S7/285 ,  H04B1/18 ,  H03K19/177 ,  G01R19/10 ,  H02H9/02

Abstract: A digital input receiver system comprises a first input receiver having a first current limiter input, and a first voltage comparator input coupled to a first node. A first resistor is coupled between the first node and the first current limiter input. The first input receiver outputs a digital logic signal and is coupled to a second node. The receiver system further comprises a second input receiver having a second current limiter input, and a second voltage comparator input coupled to the second node. A second resistor is coupled between the second node and the second current limiter input. The second input receiver outputs a malfunction signal. The first and second input receivers are configured to limit current through the receiver system to less than an overcurrent threshold of the first and second input receivers.

公开(公告)号：US20190146543A1

公开(公告)日：2019-05-16

申请号：US15996917

申请日：2018-06-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailendra Kumar BARANWAL ,  Anant Shankar KAMATH

IPC: G05F3/26 ,  H03K19/003 ,  H03F3/16 ,  H03K19/0185

Abstract: A bandgap voltage reference is provided in quasi-parallel with a resistor in the input path of a digital input circuit. Because of the quasi-parallel nature, the current used by the digital input circuit is limited to an amount based on the value of the external resistor. The input current is split between circuitry used to provide the logic signal across the selected isolation barrier and a sink transistor so that the current remains constant. This allows the digital input circuit to accurately limit input current without needing field-side power.

公开(公告)号：US20230111096A1

公开(公告)日：2023-04-13

申请号：US17732391

申请日：2022-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rakesh HARIHARAN ,  Tarunvir SINGH ,  Anant Shankar KAMATH ,  Mark Edward WENTROBLE ,  Christopher Joseph RODRIGUES ,  Prajwala PUTTAPPA

IPC: G06F13/38 ,  G06F13/42

Abstract: In an example, a method of operating a repeater having an isolation barrier to isolate a host side of the repeater from a peripheral side of the repeater, the repeater operable to be coupled to a universal serial bus (USB), includes causing the host side to enter into a suspend mode. The method also includes, responsive to entering the suspend mode, disabling a host isolation transceiver at the host side. The method includes periodically enabling the host isolation transceiver to transmit a data signal from the host side to the peripheral side. The method includes exiting the suspend mode. The method also includes enabling the host isolation transceiver.

公开(公告)号：US20220391217A1

公开(公告)日：2022-12-08

申请号：US17521378

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward WENTROBLE ,  Anant Shankar KAMATH ,  Rakesh HARIHARAN ,  Prajwala P ,  Suzanne Mary VINING

IPC: G06F9/4401 ,  G06F13/42

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

公开(公告)号：US20220021562A1

公开(公告)日：2022-01-20

申请号：US17352663

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Sadia Arefin KHAN ,  Anant Shankar KAMATH ,  Martin STAEBLER ,  Vikas Kumar THAWANI

IPC: H04L25/02 ,  H02K11/33 ,  H02P27/08 ,  H03K19/003 ,  H03K19/0175

Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.