公开(公告)号：US20250062678A1

公开(公告)日：2025-02-20

申请号：US18425138

申请日：2024-01-29

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatraman ,  Vikram Gakhar ,  Nischal R ,  Amrutheshwara Rao KV ,  Madhura Nasare ,  Naman Bafna

IPC: H02M1/088 ,  H02M3/158

Abstract: Described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. A second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. A first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. A second logic circuit has inputs coupled to the first comparator output, and to the first logic output. A variable resistance circuit has an output coupled to a mode detection output. An amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. A duty cycle generation circuit provides a respective pulse width modulation (PWM) signal at each of its respective duty cycle outputs.

公开(公告)号：US20250116728A1

公开(公告)日：2025-04-10

申请号：US18585853

申请日：2024-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nischal R ,  Dattatreya Baragur SURYANARAYANA ,  Bikash PRADHAN ,  Vikram GAKHAR ,  VishnuVardhan REDDY J ,  Preetam TADEPARTHY

IPC: G01R31/54 ,  H02H7/12 ,  H02M3/335

Abstract: An example multiphase power converter circuit includes a first power stage is configured to provide a first phase output signal at a first switching output based on a first control signal. The first power stage includes first open fault detection circuitry configured to disable detecting and/or reporting of an open fault condition responsive to the first control signal. A second power stage is configured to provide a second phase output signal at a second switching output based on a second control signal. The second power stage includes second open fault detection circuitry configured to enable detecting and/or reporting of the open fault condition responsive to the second control signal having a value to turn off the second power stage. The second open fault detection circuitry is further configured to detect the open fault condition based on a voltage at the second switching output.