公开(公告)号：US20210126645A1

公开(公告)日：2021-04-29

申请号：US16891011

申请日：2020-06-02

Applicant: Texas Instruments Incorporated

Inventor： Paul Stulik

IPC: H03M1/46 ,  H03M1/80 ,  H03M1/12

Abstract: Circuits and methods for minimizing charge losses due to negative transient voltage at summing terminals of an analog to digital converter (ADC) are disclosed. The ADC is coupled to a multi-bit digital to analog converter (DAC) at the summing terminals. The ADC and the DAC include PMOS and NMOS transistors whose timing are controlled to reduce charge losses. The PMOS transistors are turned ON before the NMOS transistors. Also, the PMOS transistor of the ADC is turned ON at a slower rate than the PMOS transistors of the DAC.

公开(公告)号：US10187077B2

公开(公告)日：2019-01-22

申请号：US15927510

申请日：2018-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Paul Stulik

IPC: H03M1/12 ,  H02M3/07 ,  H03M1/08 ,  H03M1/06 ,  H03M1/40

Abstract: An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

公开(公告)号：US09960782B2

公开(公告)日：2018-05-01

申请号：US15260602

申请日：2016-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Paul Stulik

IPC: H03M1/12 ,  H02M3/07 ,  H03M1/08 ,  H03M1/06 ,  H03M1/40

CPC classification number: H03M1/124 ,  H02M3/07 ,  H03M1/06 ,  H03M1/0863 ,  H03M1/403

Abstract: An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

公开(公告)号：US11038519B2

公开(公告)日：2021-06-15

申请号：US16891011

申请日：2020-06-02

Applicant: Texas Instruments Incorporated

Inventor： Paul Stulik

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/80

Abstract: Circuits and methods for minimizing charge losses due to negative transient voltage at summing terminals of an analog to digital converter (ADC) are disclosed. The ADC is coupled to a multi-bit digital to analog converter (DAC) at the summing terminals. The ADC and the DAC include PMOS and NMOS transistors whose timing are controlled to reduce charge losses. The PMOS transistors are turned ON before the NMOS transistors. Also, the PMOS transistor of the ADC is turned ON at a slower rate than the PMOS transistors of the DAC.

公开(公告)号：US11587864B2

公开(公告)日：2023-02-21

申请号：US17540447

申请日：2021-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

公开(公告)号：US11222841B2

公开(公告)日：2022-01-11

申请号：US16561593

申请日：2019-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.