公开(公告)号：US20190259827A1

公开(公告)日：2019-08-22

申请号：US15902829

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  C23C16/455 ,  H01G4/018 ,  H01L21/677

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

公开(公告)号：US20190259826A1

公开(公告)日：2019-08-22

申请号：US15902764

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/06 ,  H01G4/08 ,  H01L27/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US12002846B2

公开(公告)日：2024-06-04

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arlon Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US11569342B2

公开(公告)日：2023-01-31

申请号：US16820549

申请日：2020-03-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  C23C16/455 ,  H01L21/677 ,  H01G4/018 ,  H03M1/12

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

公开(公告)号：US12170310B2

公开(公告)日：2024-12-17

申请号：US16453796

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Guruvayurappan S. Mathur ,  Abbas Ali ,  Poornika Fernandes ,  Bhaskar Srinivasan ,  Darrell R. Krumme ,  Joao Sergio Afonso ,  Shih-Chang Chang ,  Shariq Arshad

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L49/02

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

公开(公告)号：US11171200B2

公开(公告)日：2021-11-09

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arion Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US11670671B2

公开(公告)日：2023-06-06

申请号：US17181485

申请日：2021-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

CPC classification number: H01L28/40 ,  H01G4/085 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/0629 ,  H01L29/0649

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US11239230B2

公开(公告)日：2022-02-01

申请号：US16665288

申请日：2019-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Guruvayurappan Mathur ,  Poornika Fernandes

IPC: H01L27/07 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

公开(公告)号：US10964778B2

公开(公告)日：2021-03-30

申请号：US15902764

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US20200219969A1

公开(公告)日：2020-07-09

申请号：US16820549

申请日：2020-03-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  C23C16/455 ,  H01L21/677 ,  H01G4/018

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.