公开(公告)号：US20240290641A1

公开(公告)日：2024-08-29

申请号：US18175718

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Hao Yang ,  John K. Arch

IPC: H01L21/67 ,  H01L29/06

CPC classification number: H01L21/67259 ,  H01L29/0649

Abstract: A method includes performing a fabrication process that fabricates a wafer having an upper region and unit areas arranged in rows along a first direction and columns along an orthogonal second direction and respective scribe streets between adjacent unit areas to: form first and second electrical components on or in the upper region in respective unit areas or scribe streets, the first and second electrical components spaced apart from one another and including structural features with different respective first and second spacing distances along the first direction.

公开(公告)号：US11587864B2

公开(公告)日：2023-02-21

申请号：US17540447

申请日：2021-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

公开(公告)号：US11222841B2

公开(公告)日：2022-01-11

申请号：US16561593

申请日：2019-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.