公开(公告)号：US20230061062A1

公开(公告)日：2023-03-02

申请号：US17463115

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Rakesh Dimri ,  Somasekar J ,  Mohammad Asif Farooqui

IPC: H03K19/08

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.

公开(公告)号：US12211850B2

公开(公告)日：2025-01-28

申请号：US17514580

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Dimri ,  Badarish Mohan Subbannavar ,  Somasekar J

IPC: H01L27/118

Abstract: An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

公开(公告)号：US11978738B2

公开(公告)日：2024-05-07

申请号：US15840335

申请日：2017-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rakesh Dimri ,  Senthil Kumar Sundaramoorthy

IPC: H01L27/118 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5221 ,  H01L23/5286 ,  H01L23/53271 ,  H01L27/0207 ,  H01L21/823475 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A device comprising a semiconductor substrate. The device also comprising a digital block defined on the substrate and having multiple electronic elements. The device also comprises first and second poly layers coupling to the multiple electronic elements, the first and second poly layers extending in parallel through the digital block in a first direction. The device further comprising a third poly layer coupled to the first poly layer and extending through a gap in the second poly layer in a second direction orthogonal to the first direction poly.

公开(公告)号：US11626879B2

公开(公告)日：2023-04-11

申请号：US17463115

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Rakesh Dimri ,  Somasekar J ,  Mohammad Asif Farooqui

IPC: H03K19/08

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.