公开(公告)号：US20230061062A1

公开(公告)日：2023-03-02

申请号：US17463115

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Rakesh Dimri ,  Somasekar J ,  Mohammad Asif Farooqui

IPC: H03K19/08

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.

公开(公告)号：US20180331675A1

公开(公告)日：2018-11-15

申请号：US16042194

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/012 ,  H03K19/094 ,  H03K3/3562 ,  H03K19/00

CPC classification number: H03K3/3562 ,  H03K3/012 ,  H03K3/356147 ,  H03K3/356156 ,  H03K3/356191 ,  H03K3/35625 ,  H03K19/0002 ,  H03K19/09429

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

公开(公告)号：US10056882B2

公开(公告)日：2018-08-21

申请号：US15391465

申请日：2016-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/012 ,  H03K3/3562 ,  H03K19/00 ,  H03K19/094

CPC classification number: H03K3/3562 ,  H03K3/012 ,  H03K3/356147 ,  H03K3/356156 ,  H03K3/356191 ,  H03K3/35625 ,  H03K19/0002 ,  H03K19/09429

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

公开(公告)号：US11043937B1

公开(公告)日：2021-06-22

申请号：US16713343

申请日：2019-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Arnab Khawas ,  Suvam Nandi

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US09471278B2

公开(公告)日：2016-10-18

申请号：US14496767

申请日：2014-09-25

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: G06F7/501 ,  G06F7/50 ,  H03K19/20 ,  H03K19/00

CPC classification number: G06F7/50 ,  G06F7/501 ,  H03K19/0013 ,  H03K19/20

Abstract: A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

Abstract translation: 公开了一种利用低面积的全加器。 全加器包括一个异或逻辑电路。 异或逻辑电路接收第一输入和第二输入。 第一反相器接收异或逻辑电路的输出并产生异或输出。 进位发生电路接收异或逻辑电路的输出，异或输出和第三输入。 进位发生电路产生反转进位。 第二反相器耦合到进位发生电路，并产生接收反向进位的进位。 和产生电路接收异或逻辑电路的输出，异或输出和第三输入。 和产生电路产生一个反相和。 第三反相器耦合到和产生电路，并在接收到反相和时产生和。

公开(公告)号：US20160094204A1

公开(公告)日：2016-03-31

申请号：US14498412

申请日：2014-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372

Abstract: The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a flip-flop input and a clock input. A master latch is coupled to an output of the tri-state inverter and provides a control signal to the tri-state inverter. The control signal activates the tri-state inverter. A slave latch receives an output of the master latch and the control signal. An output inverter is coupled to an output of the slave latch and generates a flip-flop output.

Abstract translation: 本公开提供了一种触发器，其由于晶体管数量减少而利用低功率。 触发器包括接收触发器输入和时钟输入的三态反相器。 主锁存器耦合到三态反相器的输出，并向三态反相器提供控制信号。 控制信号激活三态变频器。 从锁存器接收主锁存器和控制信号的输出。 输出反相器耦合到从锁存器的输出并产生触发器输出。

公开(公告)号：US11509294B2

公开(公告)日：2022-11-22

申请号：US17319505

申请日：2021-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Arnab Khawas ,  Suvam Nandi

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US09350327B2

公开(公告)日：2016-05-24

申请号：US14498412

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372

Abstract: The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a flip-flop input and a clock input. A master latch is coupled to an output of the tri-state inverter and provides a control signal to the tri-state inverter. The control signal activates the tri-state inverter. A slave latch receives an output of the master latch and the control signal. An output inverter is coupled to an output of the slave latch and generates a flip-flop output.

Abstract translation: 本公开提供了一种触发器，其由于晶体管数量减少而利用低功率。 触发器包括接收触发器输入和时钟输入的三态反相器。 主锁存器耦合到三态反相器的输出，并向三态反相器提供控制信号。 控制信号激活三态变频器。 从锁存器接收主锁存器和控制信号的输出。 输出反相器耦合到从锁存器的输出并产生触发器输出。

公开(公告)号：US20220342634A1

公开(公告)日：2022-10-27

申请号：US17241753

申请日：2021-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Nandini Bollam ,  Badarish Mohan Subbannavar

IPC: G06F7/501 ,  H03K17/687

Abstract: Examples of compact, high performance full adder circuits and methods of forming and operating the same are provided. In an example, a full adder comprises a first stage, a second stage and a third stage. The first stage has a first output at which a first reused signal is generated and a second output at which a second reused signal is generated. The second stage has a first reused signal input to which the first reused signal is applied, a second reused signal input to which the second reused signal is applied, and a sum output at which a sum signal is generated. The third stage has a third reused signal input to which the first reused signal is applied, a fourth reused signal input to which the second reused signal is applied, and a carry-out output at which a carry-out signal is generated. In some examples, the first stage includes a transistor stack and an inverter that share a transistor.

公开(公告)号：US09425771B2

公开(公告)日：2016-08-23

申请号：US14498048

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35606 ,  H03K3/35625

Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.

Abstract translation: 公开了一种使用低面积的触发器。 触发器包括三态反相器，其接收触发器输入，时钟输入和反相时钟输入。 主锁存器接收三态反相器的输出。 主锁存器包括一个公共的逆变器。 从锁存器耦合到主锁存器。 公共逆变器在主锁存器和从锁存器之间共享。 输出反相器耦合到公共反相器并产生触发器输出。