公开(公告)号：US20210135675A1

公开(公告)日：2021-05-06

申请号：US17146510

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya SAHU ,  Rittu SACHDEV

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/095

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

公开(公告)号：US20240305321A1

公开(公告)日：2024-09-12

申请号：US18668397

申请日：2024-05-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Pranav SINHA ,  Mayank Kumar SINGH ,  Rittu SACHDEV ,  Karan Singh BHATIA ,  Shailesh JOSHI ,  Indu PRATHAPAN

IPC: H04B1/00 ,  H04B1/04 ,  H04B1/10 ,  H04B1/69

CPC classification number: H04B1/0075 ,  H04B1/04 ,  H04B1/1036 ,  H04B1/69 ,  H04B2001/0408 ,  H04B2001/1045 ,  H04B2001/1063 ,  H04B2001/6912

Abstract: In a radar system, an intermediate frequency amplifier (IFA) is configured with two high-pass filter stages, each having an amplifier and a configurable impedance component. A control signal is activated as the radar system begins to transmit a chirp signal to lower the impedance of the configurable impedance components during an initial portion of the chirp transmission to achieve faster settling of the IFA output signal. After the initial portion, the control signal deactivates while transmission of the chirp continues to increase the impedance of the configurable impedance components to a level sufficient to effectively perform filtering of unwanted signals received by the radar system.

公开(公告)号：US20230396259A1

公开(公告)日：2023-12-07

申请号：US18452196

申请日：2023-08-18

Applicant: Texas Instruments Incorporated

Inventor： Debapriya SAHU ,  Rittu SACHDEV

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/095

CPC classification number: H03L7/093 ,  H03L7/083 ,  H03L7/095

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

公开(公告)号：US20230216528A1

公开(公告)日：2023-07-06

申请号：US17566047

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Pranav SINHA ,  Mayank Kumar SINGH ,  Rittu SACHDEV ,  Karan Singh BHATIA ,  Shailesh JOSHI ,  Indu PRATHAPAN

IPC: H04B1/00 ,  H04B1/10 ,  H04B1/04 ,  H04B1/69

CPC classification number: H04B1/0075 ,  H04B1/1036 ,  H04B1/04 ,  H04B1/69 ,  H04B2001/6912 ,  H04B2001/0408 ,  H04B2001/1063 ,  H04B2001/1045

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

公开(公告)号：US20220360269A1

公开(公告)日：2022-11-10

申请号：US17865808

申请日：2022-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya SAHU ,  Rittu SACHDEV

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/095

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.