公开(公告)号：US20150015438A1

公开(公告)日：2015-01-15

申请号：US14037052

申请日：2013-09-25

Applicant: Texas Instruments Incorporated

Inventor： Karthik SUBBURAJ ,  Karthik Ramasubramanian ,  Jawaharlal Tangudu

IPC: G01S19/24

CPC classification number: G01S19/24 ,  G01S19/246 ,  G01S19/25

Abstract: A method of acquiring a satellite signal in a GNSS receiver includes multiplying a received signal with a hypothesized doppler frequency signal to generate a frequency shifted signal. A PN code sequence signal is multiplied with the frequency shifted signal to generate a PN wiped signal. A windowing function signal is multiplied with the PN wiped signal to generate a windowed signal. The windowed signal is integrated coherently for a first predefined time to generate a coherent accumulated data.

Abstract translation: 在GNSS接收机中获取卫星信号的方法包括将接收信号与假设的多普勒频率信号相乘以产生频移信号。 PN码序列信号与频移信号相乘以产生PN擦除信号。 加窗功能信号与PN擦除信号相乘以产生加窗信号。 窗口信号被相干地整合在第一预定义时间以产生相干累积数据。

公开(公告)号：US20240345805A1

公开(公告)日：2024-10-17

申请号：US18753107

申请日：2024-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.

公开(公告)号：US20230017031A1

公开(公告)日：2023-01-19

申请号：US17498342

申请日：2021-10-11

Applicant: Texas Instruments Incorporated

Inventor： Shankar Ram NARAYANA MOORTHY ,  Karthik SUBBURAJ ,  Shailesh JOSHI ,  Piyush SONI

IPC: G01S7/28 ,  G01S7/35

Abstract: A non-transitory computer-readable storage device stores machine instructions which, when executed by a processor, cause the processor to determine a chirp period Tc for radar chirps in a radar frame. The chirp period Tc comprises a rising period Trise and a falling period Tfall. The processor determines, for each radar chirp in the radar frame, a corresponding randomized frequency characteristic during Tfall, and causes a radar sensor circuit to generate the radar chirps in the radar frame based on Tc, Trise, Tfall, and the corresponding randomized frequency characteristics. In some implementations, the machine instructions to determine the corresponding randomized frequency characteristic comprise machine instructions to determine a frequency step having a frequency f_step and a period Tstep. At least one of the frequency f_step and the period Tstep is dithered across radar chirps in the radar frame.

公开(公告)号：US20220366004A1

公开(公告)日：2022-11-17

申请号：US17357919

申请日：2021-06-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh JOSHI ,  Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN

IPC: G06F17/14

Abstract: A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.

公开(公告)号：US20200284874A1

公开(公告)日：2020-09-10

申请号：US16294764

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shankar Ram NARAYANA MOORTHY ,  Karthik SUBBURAJ ,  Anil KV KUMAR

IPC: G01S7/35 ,  G01S13/58

Abstract: A method for a radar system includes transmitting, by a transmit channel of the radar system, a frame comprising first, second, and third chirps. Each chirp has a chirp start frequency, and the chirp start frequency of the transmitted chirps is dithered. The method also includes receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency (IF) signal.

公开(公告)号：US20240094335A1

公开(公告)日：2024-03-21

申请号：US18526250

申请日：2023-12-01

Applicant: Texas Instruments Incorporated

Inventor： Shankar Ram NARAYANA MOORTHY ,  Karthik SUBBURAJ ,  Shailesh JOSHI ,  Piyush SONI

IPC: G01S7/28 ,  G01S7/35

CPC classification number: G01S7/2813 ,  G01S7/352

Abstract: Non-transitory computer-readable mediums and systems are provided in which a portion of each chirp of a series of chirps is held at an offset frequency for a period of time, and in which the offset frequency, the period of time or both is varied or dithered across the chirps of the series of chirps. The portion of a chirp that is held at an offset frequency for a period of time may be a non-active portion of the chirp, during which the chirp is not sampled. In some implementations, the portion of a chirp that is held at an offset frequency for a period of time is during a falling portion of the chirp, which may be at the beginning of the falling portion, or at the end of the falling portion immediately before a rise portion of a succeeding chirp.

公开(公告)号：US20230216528A1

公开(公告)日：2023-07-06

申请号：US17566047

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Pranav SINHA ,  Mayank Kumar SINGH ,  Rittu SACHDEV ,  Karan Singh BHATIA ,  Shailesh JOSHI ,  Indu PRATHAPAN

IPC: H04B1/00 ,  H04B1/10 ,  H04B1/04 ,  H04B1/69

CPC classification number: H04B1/0075 ,  H04B1/1036 ,  H04B1/04 ,  H04B1/69 ,  H04B2001/6912 ,  H04B2001/0408 ,  H04B2001/1063 ,  H04B2001/1045

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

公开(公告)号：US20220156044A1

公开(公告)日：2022-05-19

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F9/355 ,  G06F17/14 ,  G06F16/901

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US20220120884A1

公开(公告)日：2022-04-21

申请号：US17351654

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN ,  Shailesh JOSHI ,  Kameswaran VENGATTARAMANE ,  Indu PRATHAPAN

IPC: G01S13/04 ,  G01S7/35 ,  G06F17/14 ,  G06F16/22 ,  G06F16/901

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

公开(公告)号：US20200309939A1

公开(公告)日：2020-10-01

申请号：US16363719

申请日：2019-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Sandeep RAO ,  Sriram MURALI ,  Karthik RAMASUBRAMANIAN

IPC: G01S13/58 ,  G01S7/35

Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.