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公开(公告)号：US20220069834A1
公开(公告)日：2022-03-03
申请号：US17007887
申请日：2020-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya SAHU , Pranav SINHA , Meghna AGRAWAL
Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.
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公开(公告)号：US20210135675A1
公开(公告)日：2021-05-06
申请号：US17146510
申请日：2021-01-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya SAHU , Rittu SACHDEV
Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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公开(公告)号：US20150326236A1
公开(公告)日：2015-11-12
申请号：US14709759
申请日：2015-05-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Krishnaswamy THIAGARAJAN , Jagdish Chand GOYAL , Srikanth MANIAN , Debapriya SAHU
CPC classification number: H03L7/1976 , H03L7/0814 , H03L7/1974 , H03L2207/10 , H04B1/40 , H04L7/033 , H04L7/0331
Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.
Abstract translation: 一个抑制整数边界杂散的分数N频率合成器。 频率合成器包括分数N锁相环（PLL）和参考频率缩放器。 参考频率缩放器耦合到PLL的参考时钟输入，参考频率缩放器包括可编程分频器和与可编程分频器串联连接的可编程倍频器。 分频器和乘法器中的每一个被配置为通过可编程整数值来缩放提供给PLL的参考频率。
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公开(公告)号：US20230094295A1
公开(公告)日：2023-03-30
申请号：US17489163
申请日：2021-09-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rohit CHATTERJEE , Debapriya SAHU
Abstract: A transmitter comprises an antenna array demultiplexor having a first input for an output signal, a second input for a control signal, a first output coupled to a first output pin, and a second output coupled to a second output pin. The antenna array demultiplexor provides the output signal to the first or second output based on the control signal. The first and second output pins are coupled to first and second antennae, respectively. In some implementations, the transmitter includes a transformer and a capacitor coupled in parallel between the first and second output pins, and the antenna array demultiplexor comprises a first switch coupled between the first output pin and a first ground pin, and a second switch coupled between the second output pin and a second ground pin. The first switch receives a second control signal, and the second switch receives an inverse of the second control signal.
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公开(公告)号：US20220360269A1
公开(公告)日：2022-11-10
申请号：US17865808
申请日：2022-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya SAHU , Rittu SACHDEV
Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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Patent Agency Ranking
公开(公告)号：US20240313810A1
公开(公告)日：2024-09-19
申请号：US18669603
申请日：2024-05-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rohit CHATTERJEE , Debapriya SAHU
CPC classification number: H04B1/0064 , H04B1/0475 , H04B1/0483 , H04B2001/0408
Abstract: A transmitter comprises an antenna array demultiplexor having a first input for an output signal, a second input for a control signal, a first output coupled to a first output pin, and a second output coupled to a second output pin. The antenna array demultiplexor provides the output signal to the first or second output based on the control signal. The first and second output pins are coupled to first and second antennae, respectively. In some implementations, the transmitter includes a transformer and a capacitor coupled in parallel between the first and second output pins, and the antenna array demultiplexor comprises a first switch coupled between the first output pin and a first ground pin, and a second switch coupled between the second output pin and a second ground pin. The first switch receives a second control signal, and the second switch receives an inverse of the second control signal.
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公开(公告)号：US20240267053A1
公开(公告)日：2024-08-08
申请号：US18639466
申请日：2024-04-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Meghna AGRAWAL , Debapriya SAHU
CPC classification number: H03M1/0617 , H03M3/464
Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.
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公开(公告)号：US20220407537A1
公开(公告)日：2022-12-22
申请号：US17893076
申请日：2022-08-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya SAHU , Pranav SINHA , Meghna AGRAWAL
Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
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公开(公告)号：US20240113724A1
公开(公告)日：2024-04-04
申请号：US18535445
申请日：2023-12-11
Applicant: Texas Instruments Incorporated
Inventor： Debapriya SAHU , Pranav SINHA , Meghna AGRAWAL
CPC classification number: H03M1/462 , H03M1/0626 , H03M1/182 , H03M1/468
Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
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公开(公告)号：US20230396259A1
公开(公告)日：2023-12-07
申请号：US18452196
申请日：2023-08-18
Applicant: Texas Instruments Incorporated
Inventor： Debapriya SAHU , Rittu SACHDEV
Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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