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    STREAMING ADDRESS GENERATION
    1.
    发明申请
    STREAMING ADDRESS GENERATION 有权

    公开(公告)号：US20210157585A1

    公开(公告)日：2021-05-27

    申请号：US17164448

    申请日：2021-02-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

    IPC: G06F9/30 ,  G06F12/0811

    Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

    LOOK UP TABLE WITH DATA ELEMENT PROMOTION
    2.
    发明申请
    LOOK UP TABLE WITH DATA ELEMENT PROMOTION 审中-公开

    公开(公告)号：US20190205132A1

    公开(公告)日：2019-07-04

    申请号：US15940283

    申请日：2018-03-29

    Applicant: Texas Instruments Incorporated

    Inventor： Duc BUI ,  Dheera BALASUBRAMANIAN ,  Naveen BHORIA ,  Sahithi KRISHNA

    IPC: G06F9/30 ,  G06F17/30

    Abstract: Disclosed embodiments relate to look up table operations implemented in a digital data processor. A look up table read instruction recalls data elements of a specified data size from table(s) and stores recalled data elements in successive slots in a destination register. Disclosed embodiments promote data elements to a larger size with selected sign or zero extension. A source operand register stores vector offsets from a table start address. A destination operand stores the results of the look up table read. The look up table instruction implies a base address register and a configuration register. The base address register stores a table base address. The configuration register sets various look up table read operation parameters.

    STREAMING ADDRESS GENERATION
    4.
    发明申请
    STREAMING ADDRESS GENERATION 审中-公开

    公开(公告)号：US20200371789A1

    公开(公告)日：2020-11-26

    申请号：US16422324

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

    IPC: G06F9/30 ,  G06F12/0811

    Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

    STREAMING ADDRESS GENERATION
    5.
    发明申请
    STREAMING ADDRESS GENERATION 有权

    公开(公告)号：US20250013467A1

    公开(公告)日：2025-01-09

    申请号：US18892682

    申请日：2024-09-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

    IPC: G06F9/30 ,  G06F12/0811

    Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

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