公开(公告)号：US20230015163A1

公开(公告)日：2023-01-19

申请号：US17946113

申请日：2022-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang BUI ,  Alan L. DAVIS ,  Dheera Balasubramanian SAMUDRALA ,  Timothy David ANDERSON

IPC: G06F9/30 ,  G06F9/38

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

公开(公告)号：US20220276965A1

公开(公告)日：2022-09-01

申请号：US17744810

申请日：2022-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

公开(公告)号：US20220156193A1

公开(公告)日：2022-05-19

申请号：US17590749

申请日：2022-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Timothy David ANDERSON

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

公开(公告)号：US20210365374A1

公开(公告)日：2021-11-25

申请号：US16882344

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  Pramod Kumar SWAMI ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F12/0811 ,  G06F12/10

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

公开(公告)号：US20200371964A1

公开(公告)日：2020-11-26

申请号：US16882403

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F12/0811

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

公开(公告)号：US20200371924A1

公开(公告)日：2020-11-26

申请号：US16882329

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  David Matthew THOMPSON

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F9/30 ,  G06F13/16

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

公开(公告)号：US20250013467A1

公开(公告)日：2025-01-09

申请号：US18892682

申请日：2024-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

IPC: G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20240152385A1

公开(公告)日：2024-05-09

申请号：US18411763

申请日：2024-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

公开(公告)号：US20230359385A1

公开(公告)日：2023-11-09

申请号：US18353181

申请日：2023-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Soujanya NARNUR

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

CPC classification number: G06F3/0652 ,  G06F13/1668 ,  G06F3/0673 ,  G06F3/0604 ,  G06F15/8076

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US20230214220A1

公开(公告)日：2023-07-06

申请号：US18120601

申请日：2023-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

IPC: G06F9/30 ,  G06F12/0811

CPC classification number: G06F9/3016 ,  G06F9/30065 ,  G06F12/0811 ,  G06F9/30098

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.