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    MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR
    3.
    发明申请
    MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR 有权

    公开(公告)号：US20210247980A1

    公开(公告)日：2021-08-12

    申请号：US17241198

    申请日：2021-04-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Kai CHIRCA

    IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

    SYSTEM AND METHOD FOR ADDRESSING DATA IN MEMORY
    4.
    发明公开
    SYSTEM AND METHOD FOR ADDRESSING DATA IN MEMORY 审中-公开

    公开(公告)号：US20240103863A1

    公开(公告)日：2024-03-28

    申请号：US18529034

    申请日：2023-12-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Kai CHIRCA

    IPC: G06F9/30

    CPC classification number: G06F9/30123 ,  G06F9/30101 ,  G06F9/30134

    Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

    STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES
    5.
    发明申请
    STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES 有权

    公开(公告)号：US20220188115A1

    公开(公告)日：2022-06-16

    申请号：US17557712

    申请日：2021-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph ZBICIAK

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F12/0875

    Abstract: A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.

    VECTOR FLOATING-POINT CLASSIFICATION
    6.
    发明申请
    VECTOR FLOATING-POINT CLASSIFICATION 审中-公开

    公开(公告)号：US20200371794A1

    公开(公告)日：2020-11-26

    申请号：US16422688

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph ZBICIAK ,  Brett L. HUBER ,  Duc BUI

    IPC: G06F9/30 ,  G06K9/62

    Abstract: A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.

    VECTOR FLOATING-POINT SCALE
    7.
    发明申请
    VECTOR FLOATING-POINT SCALE 审中-公开

    公开(公告)号：US20200371784A1

    公开(公告)日：2020-11-26

    申请号：US16422754

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK

    IPC: G06F9/30

    Abstract: A method to scale source data in a processor in response to a vector floating-point scale instruction includes specifying a first source register containing the source data, a second source register containing scale values, and a destination register to store scaled source data. The first source register includes a plurality of lanes that each contains a floating-point value and the second source register and the destination register each includes a plurality of lanes corresponding to the lanes of the first source register. The method includes executing the vector floating-point scale instruction by, for each lane in the first source register adding the scale value in the corresponding lane of the second source register to an exponent field of the floating-point value in the lane of the first source register to create a scaled floating-point value, and storing the scaled floating-point value in the corresponding lane of the destination register.

    STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES
    8.
    发明申请
    STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES 审中-公开

    公开(公告)号：US20190324754A1

    公开(公告)日：2019-10-24

    申请号：US16458756

    申请日：2019-07-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph ZBICIAK

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F12/0875

    Abstract: A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.

    STREAMING ADDRESS GENERATION
    9.
    发明申请
    STREAMING ADDRESS GENERATION 有权

    公开(公告)号：US20250013467A1

    公开(公告)日：2025-01-09

    申请号：US18892682

    申请日：2024-09-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

    IPC: G06F9/30 ,  G06F12/0811

    Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

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