公开(公告)号：US11734382B2

公开(公告)日：2023-08-22

申请号：US17331215

申请日：2021-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Sai Ram Prakash Jayanthi

IPC: G06F17/14 ,  G06F7/76 ,  G06F13/28

CPC classification number: G06F17/142 ,  G06F7/768 ,  G06F13/287

Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

公开(公告)号：US11170071B2

公开(公告)日：2021-11-09

申请号：US16221470

申请日：2018-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Sai Ram Prakash Jayanthi

IPC: G06F17/14 ,  G06F7/76 ,  G06F13/28

Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.