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    Bitonic sorting accelerator
    2.
    发明授权
    Bitonic sorting accelerator 有权

    公开(公告)号：US10901692B2

    公开(公告)日：2021-01-26

    申请号：US16237447

    申请日：2018-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

    IPC: G06F7/24 ,  G06F5/06

    Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

    Infrastructure integrity checking
    5.
    发明授权
    Infrastructure integrity checking 有权

    公开(公告)号：US11366715B2

    公开(公告)日：2022-06-21

    申请号：US17027888

    申请日：2020-09-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Desmond Fernandes ,  Indu Prathapan ,  Jasbir Singh ,  Prathap Srinivasan ,  Rishav Karki

    IPC: G06F11/10 ,  G06F13/40 ,  G06F11/07

    Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

    Save-restore in integrated circuits
    6.
    发明授权
    Save-restore in integrated circuits 有权

    公开(公告)号：US10747466B2

    公开(公告)日：2020-08-18

    申请号：US16235897

    申请日：2018-12-28

    Applicant: Texas Instruments Incorporated

    Inventor： Puneet Sabbarwal ,  Indu Prathapan

    IPC: G06F3/06 ,  G06F30/30

    Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

    Peak-to-average power reduction using guard tone filtering
    7.
    发明授权
    Peak-to-average power reduction using guard tone filtering 有权

    公开(公告)号：US09967123B1

    公开(公告)日：2018-05-08

    申请号：US15426464

    申请日：2017-02-07

    Applicant: Texas Instruments Incorporated

    Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

    IPC: H04L27/00 ,  H04L27/26

    CPC classification number: H04L27/2615 ,  H04L27/2634

    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

    Error correction hardware with fault detection
    8.
    发明授权
    Error correction hardware with fault detection 有权

    公开(公告)号：US09904595B1

    公开(公告)日：2018-02-27

    申请号：US15244739

    申请日：2016-08-23

    Applicant: Texas Instruments Incorporated

    Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

    IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/52

    Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

    Bitonic sorting accelerator
    9.
    发明授权
    Bitonic sorting accelerator 有权

    公开(公告)号：US12141544B2

    公开(公告)日：2024-11-12

    申请号：US18335452

    申请日：2023-06-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

    IPC: G06F7/24 ,  G06F5/06

    Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

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