公开(公告)号：US10163680B1

公开(公告)日：2018-12-25

申请号：US15709039

申请日：2017-09-19

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Scott Kelly Montgomery

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/74 ,  H01L29/10

Abstract: A method of forming an IC includes forming a buried layer (BL) doped a second type in a substrate doped a first type. Deep trenches are etched including narrower inner trench rings and wider outer trench rings through to the BL. A first deep sinker implanting uses ions of the second type with a first dose, a first energy, and a first tilt angle. A second deep sinker implant uses ions of the second type with a second dose that than the first energy, and a second tilt angle

公开(公告)号：US20240112947A1

公开(公告)日：2024-04-04

申请号：US17977250

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott Kelly Montgomery ,  James Todd ,  Yanbiao Pan ,  Jeffery Nilles

IPC: H01L21/762 ,  H01L27/06

CPC classification number: H01L21/76224 ,  H01L27/0629

Abstract: The present disclosure generally relates to shallow trench isolation (STI) processing with local oxidation of silicon (LOCOS), and an integrated circuit formed thereby. In an example, an integrated circuit includes a semiconductor layer, a LOCOS layer, an STI structure, and a passive circuit component. The semiconductor layer is over a substrate. The LOCOS layer is over the semiconductor layer. The STI structure extends into the semiconductor layer. The passive circuit component is over and touches the LOCOS layer.

公开(公告)号：US10886160B2

公开(公告)日：2021-01-05

申请号：US16188368

申请日：2018-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Scott Kelly Montgomery

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/74 ,  H01L29/10 ,  H01L29/423

Abstract: An electronic device, e.g. an integrated circuit, includes a semiconductor substrate having a top surface and an area of the semiconductor substrate surrounded by inner and outer trench rings. The inner trench ring includes a first dielectric liner that extends from the substrate surface to a bottom of the inner trench ring, the first dielectric liner electrically isolating an interior region of the inner trench ring from the semiconductor substrate. The outer trench ring surrounds the inner trench ring and includes a second dielectric liner that extends from the substrate surface to a bottom of the outer trench ring. The second dielectric liner includes an opening at a bottom of the outer trench ring, the opening providing a path between an interior region of the outer trench ring and the semiconductor substrate.