公开(公告)号：US20230290775A1

公开(公告)日：2023-09-14

申请号：US18317227

申请日：2023-05-15

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Yanbiao Pan

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

公开(公告)号：US20220139907A1

公开(公告)日：2022-05-05

申请号：US17086421

申请日：2020-11-01

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Yanbiao Pan

IPC: H01L27/06 ,  H01L21/8234

Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

公开(公告)号：US20210005760A1

公开(公告)日：2021-01-07

申请号：US17023639

申请日：2020-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L29/94 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US20240312984A1

公开(公告)日：2024-09-19

申请号：US18677190

申请日：2024-05-29

Applicant: Texas Instruments Incorporated

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC: H01L27/06 ,  H01L21/285

CPC classification number: H01L27/0629 ,  H01L21/28525 ,  H01L21/28556 ,  H01L28/20

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US20240112947A1

公开(公告)日：2024-04-04

申请号：US17977250

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott Kelly Montgomery ,  James Todd ,  Yanbiao Pan ,  Jeffery Nilles

IPC: H01L21/762 ,  H01L27/06

CPC classification number: H01L21/76224 ,  H01L27/0629

Abstract: The present disclosure generally relates to shallow trench isolation (STI) processing with local oxidation of silicon (LOCOS), and an integrated circuit formed thereby. In an example, an integrated circuit includes a semiconductor layer, a LOCOS layer, an STI structure, and a passive circuit component. The semiconductor layer is over a substrate. The LOCOS layer is over the semiconductor layer. The STI structure extends into the semiconductor layer. The passive circuit component is over and touches the LOCOS layer.

公开(公告)号：US11676961B2

公开(公告)日：2023-06-13

申请号：US17086421

申请日：2020-11-01

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Yanbiao Pan

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

公开(公告)号：US20210028316A1

公开(公告)日：2021-01-28

申请号：US16939823

申请日：2020-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Yanbiao Pan ,  Django Trombley

IPC: H01L29/94 ,  H01L29/66

Abstract: A semiconductor device includes an integrated trench capacitor in a substrate, with a field oxide layer on the substrate. The trench capacitor includes trenches extending into semiconductor material of the substrate, and a capacitor dielectric in the trenches on the semiconductor material. The trench capacitor further includes an electrically conductive trench-fill material on the capacitor dielectric. A portion of the capacitor dielectric extends into the field oxide layer, between a first segment of the field oxide layer over the trench-fill material and a second segment of the field oxide layer over the semiconductor material. The integrated trench capacitor has a trench contact to the trench-fill material in each of the trenches, and substrate contacts to the semiconductor material around the trenches, with no substrate contacts between the trenches.

公开(公告)号：US12027515B2

公开(公告)日：2024-07-02

申请号：US17490950

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC: H01L27/06 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/28525 ,  H01L21/28556 ,  H01L28/20

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US11742436B2

公开(公告)日：2023-08-29

申请号：US17528716

申请日：2021-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Yanbiao Pan ,  Django Trombley

IPC: H01L29/94 ,  H01L29/66

CPC classification number: H01L29/945 ,  H01L29/66181

Abstract: A semiconductor device includes an integrated trench capacitor in a substrate, with a field oxide layer on the substrate. The trench capacitor includes trenches extending into semiconductor material of the substrate, and a capacitor dielectric in the trenches on the semiconductor material. The trench capacitor further includes an electrically conductive trench-fill material on the capacitor dielectric. A portion of the capacitor dielectric extends into the field oxide layer, between a first segment of the field oxide layer over the trench-fill material and a second segment of the field oxide layer over the semiconductor material. The integrated trench capacitor has a trench contact to the trench-fill material in each of the trenches, and substrate contacts to the semiconductor material around the trenches, with no substrate contacts between the trenches.

公开(公告)号：US20230112644A1

公开(公告)日：2023-04-13

申请号：US17490950

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/285

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.