公开(公告)号：US10600495B2

公开(公告)日：2020-03-24

申请号：US15891789

申请日：2018-02-08

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Sumant Kale

IPC: G11C29/38 ,  G11C29/26 ,  G11C29/36

Abstract: In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

公开(公告)号：US20180374556A1

公开(公告)日：2018-12-27

申请号：US15891789

申请日：2018-02-08

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Sumant Kale

IPC: G11C29/38 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C29/26 ,  G11C29/36

Abstract: In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

公开(公告)号：US09702935B2

公开(公告)日：2017-07-11

申请号：US14473380

申请日：2014-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lewis Nardini ,  Sumant Kale ,  Alan Hales

IPC: G06F11/00 ,  G01R31/3185 ,  G01R31/3183

CPC classification number: G01R31/318547 ,  G01R31/318385 ,  G01R31/318575

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

公开(公告)号：US20150067426A1

公开(公告)日：2015-03-05

申请号：US14473380

申请日：2014-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lewis Nardini ,  Sumant Kale ,  Alan Hales

IPC: G01R31/3177

CPC classification number: G01R31/318547 ,  G01R31/318385 ,  G01R31/318575

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

Abstract translation: 用于测试集成电路的装置和方法。 集成电路包括要测试的电路，扫描链逻辑和测试适配器。 扫描链逻辑被配置为将测试数据传送到电路并从其测试结果。 测试适配器被配置为从自动测试控制系统接收的分组中提取测试数据，并将测试数据传送到扫描链逻辑。 测试适配器还被配置为从扫描链逻辑接收测试结果，并将测试结果打包以传输到自动测试控制系统。