公开(公告)号：USRE46193E1

公开(公告)日：2016-11-01

申请号：US14303262

申请日：2014-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Lewis Nardini ,  Jose Luis Flores ,  Abhijeet Chachad ,  Raguram Damodaran ,  Joseph R. M. Zbiciak ,  Gary Swoboda

IPC: G06F1/32

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract translation: 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

公开(公告)号：US09702935B2

公开(公告)日：2017-07-11

申请号：US14473380

申请日：2014-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lewis Nardini ,  Sumant Kale ,  Alan Hales

IPC: G06F11/00 ,  G01R31/3185 ,  G01R31/3183

CPC classification number: G01R31/318547 ,  G01R31/318385 ,  G01R31/318575

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

公开(公告)号：US20150067426A1

公开(公告)日：2015-03-05

申请号：US14473380

申请日：2014-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lewis Nardini ,  Sumant Kale ,  Alan Hales

IPC: G01R31/3177

CPC classification number: G01R31/318547 ,  G01R31/318385 ,  G01R31/318575

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

Abstract translation: 用于测试集成电路的装置和方法。 集成电路包括要测试的电路，扫描链逻辑和测试适配器。 扫描链逻辑被配置为将测试数据传送到电路并从其测试结果。 测试适配器被配置为从自动测试控制系统接收的分组中提取测试数据，并将测试数据传送到扫描链逻辑。 测试适配器还被配置为从扫描链逻辑接收测试结果，并将测试结果打包以传输到自动测试控制系统。