公开(公告)号：US20250116702A1

公开(公告)日：2025-04-10

申请号：US18588762

申请日：2024-02-27

Applicant: Texas Instruments Incorporated

Inventor： David P MAGEE ,  Bassem IBRAHIM ,  Vishnu RAVINUTHULA

IPC: G01R31/317

Abstract: A device includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. The command processing circuit has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input coupled to the reference phase output. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. The controllable clock source has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.

公开(公告)号：US20210278474A1

公开(公告)日：2021-09-09

申请号：US17194033

申请日：2021-03-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vishnu RAVINUTHULA ,  Takao OSHIDA ,  Geoffrey GRIMMER

IPC: G01R31/396 ,  H03M1/44 ,  G01R31/36 ,  H02J7/00

Abstract: An apparatus comprises a plurality of analog front ends (AFEs) adapted to be coupled to a plurality of battery cells and configured to decrease voltages received from the plurality of battery cells to produce a plurality of AFE voltages. The apparatus further comprises at least one analog-to-digital converter (ADC) coupled to the plurality of AFEs and configured to convert the plurality of AFE voltages to a plurality of corresponding digital signals. The apparatus also comprises a plurality of digital channel registers coupled to the at least one ADC and configured to store the plurality of digital signals, and a processor coupled to the at least one ADC and configured to adjust, in a round-robin calculation scheme, the plurality of digital signals based on a plurality of common mode voltage values and a plurality of common mode to differential gain values associated with the plurality of AFEs.

公开(公告)号：US20240072818A1

公开(公告)日：2024-02-29

申请号：US17900445

申请日：2022-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vishnu RAVINUTHULA

IPC: H03M1/10

CPC classification number: H03M1/1023

Abstract: A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

公开(公告)号：US20240283433A1

公开(公告)日：2024-08-22

申请号：US18171413

申请日：2023-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vishnu RAVINUTHULA ,  Tianyu Chang

IPC: H03K3/03 ,  H03K3/014 ,  H03K5/135

CPC classification number: H03K3/0315 ,  H03K3/014 ,  H03K5/135

Abstract: An oscillator circuit includes a ring oscillator and a ramp generator. The ring oscillator includes a first inverter and a second inverter. The first inverter has and a first inverter input, a first inverter output, and a first power terminal. The second inverter has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output and the second inverter output is coupled to the first inverter input. The ramp generator circuit has a ramp output coupled to the first power terminal and the second power terminal.

公开(公告)号：US20190207384A1

公开(公告)日：2019-07-04

申请号：US15856457

申请日：2017-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vishnu RAVINUTHULA ,  Simon Bevan CHURCHILL ,  Mark Allen HAMLETT ,  Eric RUDEEN

IPC: H02H9/04 ,  H02H1/00 ,  H04B17/345

CPC classification number: H02H9/04 ,  H02H1/0007 ,  H04B1/40 ,  H04B17/345

Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.