公开(公告)号：US5315545A

公开(公告)日：1994-05-24

申请号：US77299

申请日：1993-06-15

申请人： Ta-Pan Guo ,  Adi Srinivasan

发明人： Ta-Pan Guo ,  Adi Srinivasan

IPC分类号： G11C11/412 ,  G11C11/419 ,  H03K3/356 ,  G11C11/40

CPC分类号： H03K3/356156 ,  G11C11/412 ,  G11C11/419

摘要： According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-Channel MOS transistor is connected to a V.sub.SS power supply rail. The second stage has a second P-Channel MOS transistor with its source connected to the high-voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-Channel MOS transistor is connected to V.sub.SS. The gates of the first and second P-Channel MOS transistors are cross-coupled and the gates of the second and fourth N-Channel MOS transistors are cross-coupled. The gates of the first and third N-Channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-Channel MOS transistors are formed in an n-well biased at a constant power supply voltage. In a preferred embodiment the constant power supply voltage may be V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

摘要翻译： 根据本发明的第一方面，根据本发明的静态随机存取存储单元包括两个阶段。 第一级具有第一P沟道MOS晶体管，其源极连接到高压电源轨，其漏极连接到第一N沟道MOS晶体管的漏极。 第一N沟道MOS晶体管的源极连接到第二N沟道MOS晶体管的漏极。 第二N沟道MOS晶体管的源极连接到VSS电源轨。 第二级具有第二P沟道MOS晶体管，其源极连接到高压电源轨VHS，其漏极连接到第三N沟道MOS晶体管的漏极。 第三N沟道MOS晶体管的源极连接到第四N沟道MOS晶体管的漏极。 第四个N沟道MOS晶体管的源极连接到VSS。 第一和第二P沟道MOS晶体管的栅极交叉耦合，并且第二和第四N沟道MOS晶体管的栅极交叉耦合。 第一和第三N沟道MOS晶体管的栅极连接到电源轨VDD，通常为5伏。 第一和第二P沟道MOS晶体管形成为以恒定电源电压的n-阱偏置。 在优选实施例中，恒定电源电压可以是VHS。 通过第五N沟道MOS晶体管耦合到第二N沟道MOS晶体管的漏极的位线，其栅极连接到字线。