公开(公告)号：US20250113566A1

公开(公告)日：2025-04-03

申请号：US18479580

申请日：2023-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Chen ,  Tai-Jung Kuo ,  Mu-Chieh Chang ,  Zhen-Cheng Wu ,  Sung-En Lin ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.