公开(公告)号：US20240413230A1

公开(公告)日：2024-12-12

申请号：US18331305

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Mu-Chieh Chang ,  Shu Ling Liao ,  Zhen-Cheng Wu ,  Sung-En Lin ,  Tze-Liang Lee

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.

公开(公告)号：US20240413215A1

公开(公告)日：2024-12-12

申请号：US18451986

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Syun-Ming Jang ,  Mu-Chieh Chang ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes forming a stack of layers, which includes a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a spacer layer extending into the lateral recesses, trimming the spacer layer to form inner spacers, and performing a treatment process to reduce dielectric constant values of the inner spacers.

公开(公告)号：US20250113566A1

公开(公告)日：2025-04-03

申请号：US18479580

申请日：2023-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Chen ,  Tai-Jung Kuo ,  Mu-Chieh Chang ,  Zhen-Cheng Wu ,  Sung-En Lin ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.