Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications
    1.
    发明授权
    Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications 有权
    射频天线系统和高速数字数据链路,以减少无线通信的电磁干扰

    公开(公告)号:US07558348B1

    公开(公告)日:2009-07-07

    申请号:US11132757

    申请日:2005-05-18

    IPC分类号: H03D1/04

    摘要: A radio frequency antenna system and high-speed digital data link are disclosed to, among other things, reduce electromagnetic interference (“EMI”) at relatively high data rates while reducing the manufacturing complexities associated with conventional data links. In one embodiment, a radio frequency (“RF”) antenna system includes an antenna and an RF radio coupled to the antenna for receiving wireless RF signals. In particular, the RF radio is configured to digitize RF signals at a fixed data rate to form digitized data signals and to apply the digitized data signals at a variable data rate to a high-speed digital link. The variable data rate distributes the signal energy of the digitized data signals over one or more bands of frequencies, thereby beneficially altering an EMI spectral profile describing emissions that develop as the digitized data signals are transported through a channel.

    摘要翻译: 公开了一种射频天线系统和高速数字数据链路,其中除了别的以外,在相对高的数据速率下降低电磁干扰(“EMI”),同时降低了与常规数据链路相关联的制造复杂性。 在一个实施例中,射频(“RF”)天线系统包括耦合到天线的天线和RF无线电,用于接收无线RF信号。 特别地,RF无线电被配置为以固定数据速率数字化RF信号以形成数字化数据信号,并以可变数据速率将数字化数据信号应用于高速数字链路。 可变数据速率通过一个或多个频率频带分配数字化数据信号的信号能量,从而有益地改变描述随着数字化数据信号通过信道传送而发展的辐射的EMI频谱分布。

    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems
    4.
    发明授权
    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems 有权
    可变频时钟发生器,用于在射频无线通信系统中的时钟域之间同步数据速率

    公开(公告)号:US07499690B1

    公开(公告)日:2009-03-03

    申请号:US11954857

    申请日:2007-12-12

    IPC分类号: H04B1/06

    CPC分类号: H04B15/02 H04B2215/067

    摘要: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

    摘要翻译: 公开了一种系统,方法和系统,用于使用可变频率时钟发生器在可变时钟域中的时间间隔上同步平均数据速率,使其等于固定时钟域中的固定数据速率,同时减少电磁干扰,其中 其他事情。 在各种实施例中,将数据速率设置为彼此相等最小化用于在时钟域之间转换数据信号的存储。 在一个实施例中,可变频率时钟发生器包括被配置为形成可变频率时钟的相位调制器。 此外,可变时钟发生器被配置为在离散频率的范围内保持特定时间段的平均频率。 相位偏移控制器设置在固定时钟域中的固定数据速率与可变时钟域中的平均数据速率之间基本上没有偏移的平均时钟。

    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems
    6.
    发明授权
    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems 有权
    可变频时钟发生器,用于在射频无线通信系统中的时钟域之间同步数据速率

    公开(公告)号:US07389095B1

    公开(公告)日:2008-06-17

    申请号:US11132978

    申请日:2005-05-18

    IPC分类号: H04B1/06

    CPC分类号: H04B15/02 H04B2215/067

    摘要: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

    摘要翻译: 公开了一种系统,方法和系统,用于使用可变频率时钟发生器在可变时钟域中的时间间隔上同步平均数据速率,使其等于固定时钟域中的固定数据速率,同时减少电磁干扰,其中 其他事情。 在各种实施例中,将数据速率设置为彼此相等最小化用于在时钟域之间转换数据信号的存储。 在一个实施例中,可变频率时钟发生器包括被配置为形成可变频率时钟的相位调制器。 此外,可变时钟发生器被配置为在离散频率的范围内保持特定时间段的平均频率。 相位偏移控制器设置在固定时钟域中的固定数据速率与可变时钟域中的平均数据速率之间基本上没有偏移的平均时钟。

    Lamp
    7.
    外观设计
    Lamp 有权

    公开(公告)号:USD971453S1

    公开(公告)日:2022-11-29

    申请号:US29837748

    申请日:2022-05-09

    申请人: Tao Liu

    设计人: Tao Liu

    Lamp
    8.
    外观设计
    Lamp 有权

    公开(公告)号:USD971452S1

    公开(公告)日:2022-11-29

    申请号:US29837747

    申请日:2022-05-09

    申请人: Tao Liu

    设计人: Tao Liu